High frequency divider circuits and methods

• US 7,298,183 B2
• Filed: 06/01/2005
• Issued: 11/20/2007
• Est. Priority Date: 06/01/2005
• Status: Expired due to Fees

• Current Assignee: Navand Tech Co.
• Original Assignee: WiLinx Corp.
• Inventors: Mirzaei, Ahmad, Bagheri, Rahim, Djafari, Masoud, Heidari, Mohammad E
• Primary Examiner(s): Nguyen; Linh My
• Assistant Examiner(s): ALMO, KHAREEM E
• Application Number:
  US11/142,705
• Publication Number:
  US 20070024330A1
• Time in Patent Office: 902 Days
• Field of Search: 327/117, 327/115
• US Class Current: 327/115
• CPC Class Codes: H03K 23/44 using field-effect transistors H03K23/46 and H03K23/425 take precedence
• CPC Class Codes: H03K 23/52 using field-effect transistors
• CPC Class Codes: H03K 3/012 Modifications of generator to improve response time or to decrease power consumption
• CPC Class Codes: H03K 3/356 Bistable circuits

Abstract

Embodiments of the present invention include circuits and methods for dividing high frequency signals. In one embodiment the present invention includes a divider circuit comprising a differential circuit having first and second inputs to receive a first differential signal, a first frequency control input and first and second differential outputs, wherein the differential circuit has a first bias current. The divider circuit further includes a cross-coupled circuit having outputs coupled to the differential circuit outputs and a second frequency control input, wherein the cross-coupled circuit has a second bias current. Embodiments of the present invention may include circuits for controlling the relationship between bias currents and circuit parameters that vary with process or temperature or both.

Claims

1. A divider circuit comprising:

a differential circuit having first and second inputs to receive a first differential signal and first and second differential output nodes, wherein the differential circuit has a first bias current generated by a first bias generator; and

a cross-coupled circuit having a first control terminal coupled to a second output of the cross-coupled circuit and the first differential output node and a second control terminal coupled to a first output of the cross coupled circuit and the second differential output node, and wherein the cross-coupled circuit has a second bias current generated by a second bias generator that is independent of the first bias current,

wherein the differential circuit is coupled to a first transistor having a control terminal to receive a signal to be divided, and wherein the first bias generator is coupled to the differential circuit through the first transistor, and

wherein the cross-coupled circuit is coupled to a second transistor having a control terminal to receive the complement of the signal to be divided, and wherein the second bias generator is coupled to the cross-coupled circuit through the second transistor.

2. The divider circuit of claim 1 wherein the second bias current is a constant current and the first bias current is calibrated so that die ratio of the first bias current and a resistance is a constant.

3. The divider circuit of claim 1 wherein the first bias current is a constant current and the second bias current is calibrated so that the product of the second bias current and a resistance is a constant.

4. The divider circuit of claim 1 further comprising a first resistor having a first resistance coupled between the first differential output node and a supply terminal and a second resistor having a second resistance coupled between the second differential output node and the supply terminal, wherein the first bias generator is calibrated so that the ratio of the first bias current and the first or second resistance is a constant across process or temperature.

5. The divider circuit of claim 1 further comprising a first resistor having a first resistance coupled between the first differential output node and a supply terminal and a second resistor having a second resistance coupled between the second differential output node and the supply terminal, wherein the second bias generator is calibrated so that the product, of the second bias current and the first or second resistance is a constant across process or temperature.

6. The divider circuit of claim 1 further comprising a load impedance coupled between first and second differential output nodes and a supply voltage, the load impedance including a control terminal for changing the impedance between the first and second differential output nodes and the supply voltage.

7. A divider circuit comprising:

a differential circuit having first and second inputs to receive a first differential signal, and first and second differential output nodes, wherein the differential circuit is coupled to a first bias current generator; and

a cross-coupled circuit having a first control terminal coupled to a second output of the cross-coupled circuit and the first differential output node and a second control terminal coupled to a first output of the cross coupled circuit and the second differential output node, wherein the cross-coupled circuit is coupled to a second bias current generator,

wherein the differential circuit is coupled to a first transistor having a control terminal for receiving a signal to be divided, and wherein the first bias current generator is coupled to the differential circuit through the first transistor, and

wherein the cross-coupled circuit is coupled to a second transistor having a control terminal for receiving the complement of the signal to be divided, and wherein the second bias current generator is coupled to the differential circuit through the second transistor.

8. The divider circuit of claim 7 further comprising a first resistor coupled between the first differential output node and a supply terminal and a second resistor coupled between the second differential output node and the supply terminal, the first and second resistors having approximately equal resistance values, wherein the first bias current generator includes a third resistor having an approximately equal resistance value as the first and second resistors for generating a replica current, wherein, the ratio of the replica current and the resistance value of the third resistor is a constant across process or temperature.

9. The divider circuit of claim 7 further comprising a first resistor coupled between the first differential output node and a supply terminal and a second resistor coupled between the second differential output node and the supply terminal, die first and second resistors having approximately equal resistance values, wherein the first bias current generator includes a third resistor having an approximately equal resistance value as the first and second resistors for generating a replica current, wherein the product of the replica current and the resistance value of the third resistor is a constant across process or temperature.

10. The divider circuit or claim 7 wherein the first bias current generator is coupled through the first transistor in a folded cascade configuration.

11. The divider circuit of claim 7 wherein the second bias current generator is coupled through the second transistor in a folded cascade configuration.

12. A divider circuit comprising:

first and second transistors having sources coupled together to form a differential circuit, the first transistor having a first output terminal and the second transistor having a second output terminal;

first and second cross-coupled transistors having sources coupled together, the first cross-coupled transistor having a first output terminal coupled to the first output terminal of the first transistor and the second cross-coupled transistor having a second output terminal coupled to the second output terminal of the second transistor;

a first resistor coupled between the first output terminal of the first transistor and a supply terminal, the first resistor having a first resistance value;

a second resistor coupled between the second output terminal of the second transistor and the supply terminal, the second resistor having a second resistance value approximately equal to the first resistance value;

a third transistor having a control terminal coupled to a signal to be divided and a first terminal coupled to the sources of the first and second transistors, wherein the third transistor is coupled to a first bias generator that generates first bias current in the first and second transistors; and

a fourth transistor having an control terminal coupled to a complement of the signal to be divided and a first terminal coupled to the sources of the cross-coupled transistors, wherein the fourth transistor is coupled to a second bias generator that generates second bias current in the first and second cross-coupled transistors.

13. The divider circuit of claim 12, wherein the first bias generator is calibrated so that the ratio of the first bias current arid the first resistance value is constant across process or temperature.

14. The divider circuit of claim 13 wherein the first bias generator comprises a third resistor having a third resistance value approximately equal to the first resistance value, an amplifier, and a fifth transistor coupled between a first amplifier input and an output of the amplifier for generating a replica current in the fifth transistor, wherein the ratio of the replica current and the first resistance value is a constant across process or temperature.

15. The divider circuit of claim 12 wherein the second bias generator is calibrated so that the product of the second bias current and the first resistance value is a constant across process or temperature.

16. The divider circuit of claim 15 wherein the second bias generator comprises a third resistor having a third resistance value approximately equal to the first resistance value, an amplifier, and a fifth transistor coupled between a first amplifier input and an output of the amplifier for generating a replica current in the fifth transistor, wherein the product of the replica current and the first resistance value is a constant across process or temperature.

17. The divider circuit of claim 12 wherein first bias generator is coupled to the control terminal of the third transistor and the second bias generator is coupled to the control terminal of the fourth transistor.

18. The divider circuit of claim 12 wherein first bias generator is coupled to a second terminal of the third transistor and the second bins generator is coupled to a second terminal of the fourth transistor.

19. A divider circuit comprising:

a differential circuit having first and second inputs to receive a first differential signal and first and second differential output nodes;

a cross-coupled circuit having a first control terminal coupled to a second output of the cross-coupled circuit and the first differential output node and a second control terminal coupled to a first output of the cross coupled circuit and the second differential output node;

a first transistor coupled to the differential circuit;

a second transistor coupled to the cross coupled circuit;

first bias means for biasing the differential circuit with a first bias current coupled to the differential circuit through the first transistor; and

second bias means for biasing the cross-coupled circuit with a second bias current coupled to the cross-coupled circuit through the second transistor.

20. The divider circuit of claim 19 wherein the second bias means generates a constant current and the first bias means is calibrated so that the ratio of the first bias current and a resistance is a constant.

21. The divider circuit of claim 19 wherein the first bias means generates a constant current and the second bias means is calibrated so that the product of the second bias current and a resistance is a constant.

22. The divider circuit of claim 19 further comprising means for calibrating the first bias means.

23. The divider circuit of claim 19 further comprising means for calibrating the second bias means.

24. A method of dividing a signal comprising:

receiving a first input signal to be divided on a frequency control input of a first transistor;

receiving a complement of the first input signal on a frequency control input of a second transistor;

coupling the first input signal to a differential circuit;

coupling the complement of the first input signal to a cross-coupled circuit;

coupling a first bias current through the first transistor to the differential circuit using a first bias current generator;

coupling a second bias current through the second transistor to the cross-coupled circuit using a second bias current generator;

operating the differential circuit using the first bias current; and

operating the cross-coupled circuit using the second bias current.

25. The method of claim 24 wherein the first and second bias current generators output first and second voltages, and wherein the first voltage is coupled to a control terminal of the first transistor for generating the first bias current in the differential circuit, and wherein the second voltage is coupled to a control terminal of the second transistor for generating the second bias current.

26. The method of claim 24 wherein the first and second bias current generators output first and second currents, and wherein the first voltage is coupled to a terminal of the first transistor for generating the first bias current in the differential circuit, and wherein the second current is coupled to a terminal of the second transistor for generating the second bias current.

27. The method of claim 26 wherein the first and second bias current generators are folded cascade circuits.

28. The method of claim 24 wherein the second bias current is a constant current and the first bias current is calibrated so that the ratio of the first bias current and a resistance is a constant.

29. The method of claim 24 wherein the first bias current is a constant current and the second bias current is calibrated so that the product of the second bias current and a resistance is a constant.

30. The method of claim 24 wherein the second bias current is independent of the first bias current.