Synchronous data serialization circuit
First Claim
1. A transceiver for use between interconnected high speed fiber optic communication channels, the transceiver comprising:
- an optical input system having a photo detect and driver circuit which is configured to receive an input signal from an input fiber optic channel and is configured to convert the input signal to packets of data;
a clock data recovery circuit coupled to the optical input system which is configured to receive packets of data from the optical input system and is configured to recover clock and data signals having a first frequency from the packets of data;
a demultiplexer coupled to the clock data recovery circuit which is configured to deserialize clock and data signals received from the clock data recovery circuit into a plurality of parallel signals having a second frequency lower than the first frequency;
an application specific integrated circuit coupled to the demultiplexer which is configured to perform at least one of monitoring and error correction functions at the second frequency on the plurality of parallel signals received from the demultiplexer;
a multiplexer and clock multiplication unit coupled to the application specific integrated circuit which is configured to convert the plurality of parallel signals received from the application specific integrated circuit into a signal bit stream at the first frequency, wherein the multiplexer is configured to operate to establish a phase relationship between each of the plurality of parallel signals received from the application specific integrated circuit and convert the parallel signals to a serial bit stream at the first frequency based upon the established phase relationship; and
an optical output system coupled to the multiplexer and clock multiplication unit which is configured to retransmit the single bit stream received from the multiplexer and clock multiplication unit onto an output fiber optic channel.
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Accused Products
Abstract
In accordance with the present invention a data processing circuit includes a first data path for processing first data. The first data path includes a first data storage circuit. A second data path is provided for processing second data. The second data path includes a second data storage circuit. A multiplexer having a first input coupled to the first data path and a second input coupled to the second data path receives the stored values. The multiplexer includes a select input coupled to a clock signal. A delay circuit is configured to delay storage of the second data in the second data storage circuit, wherein the first data storage circuit stores the first data in response to receiving a first timing signal, and the second data storage circuit stores the second data in response to receiving a second timing signal.
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Citations
20 Claims
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1. A transceiver for use between interconnected high speed fiber optic communication channels, the transceiver comprising:
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an optical input system having a photo detect and driver circuit which is configured to receive an input signal from an input fiber optic channel and is configured to convert the input signal to packets of data; a clock data recovery circuit coupled to the optical input system which is configured to receive packets of data from the optical input system and is configured to recover clock and data signals having a first frequency from the packets of data; a demultiplexer coupled to the clock data recovery circuit which is configured to deserialize clock and data signals received from the clock data recovery circuit into a plurality of parallel signals having a second frequency lower than the first frequency; an application specific integrated circuit coupled to the demultiplexer which is configured to perform at least one of monitoring and error correction functions at the second frequency on the plurality of parallel signals received from the demultiplexer; a multiplexer and clock multiplication unit coupled to the application specific integrated circuit which is configured to convert the plurality of parallel signals received from the application specific integrated circuit into a signal bit stream at the first frequency, wherein the multiplexer is configured to operate to establish a phase relationship between each of the plurality of parallel signals received from the application specific integrated circuit and convert the parallel signals to a serial bit stream at the first frequency based upon the established phase relationship; and an optical output system coupled to the multiplexer and clock multiplication unit which is configured to retransmit the single bit stream received from the multiplexer and clock multiplication unit onto an output fiber optic channel. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11)
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12. A delay circuit comprising:
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a first differentially connected MOS transistor; a second differentially connected MOS transistor; a first load resistor serially connected to a first inductor to form a first resistor-inductor pair; a second load resistor serially connected to a second inductor to form a second resistor-inductor pair, wherein the first resistor-inductor pair is coupled between a power supply line and the drain of the first differentially connected MOS transistor and the second resistor-inductor pair is coupled between a power supply line and the drain of the second differentially connected MOS transistor, wherein the source of the first differentially connected MOS transistor and the second differentially connected MOS transistor are coupled together through a current source to a ground, wherein a first input signal is received at a first input of the first differentially connected MOS transistor on a first differential data line, and a second input signal is received at a second input of the second differentially connected MOS transistor on a second differential data line, wherein a first output is provided at a drain of the first differentially connected MOS transistor, and a second output is provided at a drain of the second differentially connected MOS transistor, and wherein data may be either transmitted or received on the first differential data line and the second differential data line, further comprising a first parallel combination of switched capacitors connected between the first output and ground, and a second parallel combination of switched capacitors connected between the second output and ground.
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13. A delay circuit comprising:
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a first differentially connected MOS transistor; a second differentially connected MOS transistor; a first load resistor serially connected to a first inductor to form a first resistor-inductor pair; a second load resistor serially connected to a second inductor to form a second resistor-inductor pair, wherein the first resistor-inductor pair is coupled between a power supply line and the drain of the first differentially connected MOS transistor and the second resistor-inductor pair is coupled between a power supply line and the drain of the second differentially connected MOS transistor, wherein the source of the first differentially connected MOS transistor and the second differentially connected MOS transistor are coupled together through a current source to a ground, wherein a first input signal is received at a first input of the first differentially connected MOS transistor on a first differential data line, and a second input signal is received at a second input of the second differentially connected MOS transistor on a second differential data line, wherein a first output is provided at a drain of the first differentially connected MOS transistor, and a second output is provided at a drain of the second differentially connected MOS transistor, and wherein data may be either transmitted or received on the first differential data line and the second differential data line, further comprising a first parallel combination of switched capacitors connected between the first output and ground, and a second parallel combination of switched capacitors connected between the second output and ground, wherein the first parallel combination and second parallel combination of switched capacitors are selectively activated to vary delay times of the delay circuit.
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14. A method of processing a signal between interconnected high speed fiber optic communication channels, the method comprising:
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receiving an input signal from a fiber optic input channel and converting the input signal to packets of data; recovering clock and data signals having a first frequency from the packets of data; deserializing the clock and data signals into a plurality of parallel signals having a second frequency lower than the first frequency; performing monitoring and error correction functions at the second frequency on the plurality of parallel signals; establishing a phase relationship between each of the plurality of parallel signals; multiplexing the plurality of parallel signals into a serial bit stream at the first frequency based upon the established phase relationship, and retransmitting the serial bit stream received from the multiplexer and clock multiplication unit onto a fiber optic output channel. - View Dependent Claims (15, 16, 17, 18, 19, 20)
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Specification