Ground referenced pixel reset

• US 7,298,406 B2
• Filed: 01/16/2002
• Issued: 11/20/2007
• Est. Priority Date: 01/16/2002
• Status: Active Grant

• Current Assignee: Aptina Imaging Corporation (ON Semiconductor Corporation)
• Original Assignee: Micron Technology, Inc.
• Inventors: Borg, Matthew M.
• Primary Examiner(s): Vu; Ngoc-Yen
• Assistant Examiner(s): Quiett; Carramah J
• Application Number:
  US10/051,739
• Publication Number:
  US 20030133030A1
• Time in Patent Office: 2,134 Days
• Field of Search: 348/302, 348307-308, 348/310
• US Class Current: 348/308
• CPC Class Codes: H04N 25/65 applied to reset noise, e.g. KTC noise related to CMOS structures by techniques other than CDS

Abstract

A ground referenced pixel reset circuit is disclosed. The ground referenced pixel reset circuit supplies a pixel with a reset signal such that when the reset signal is asserted high, the reset signal is at a ground referenced reset voltage independent from a supply voltage. The pixel includes a photosensor, such as a photodiode, that is coupled to a ground having a same potential as the ground of the reference voltage supply. In this manner, noise caused by fluctuations in the supply voltage is reduced.

Claims

1. An image capture system, comprising:

a plurality of rows of pixels, each row comprising;

a reset line for providing a reset signal;

a plurality of pixels, each pixel comprising;

a first FET having a gate terminal coupled to a reset line, a drain terminal coupled to a supply voltage, and a source terminal coupled to a readout node; and

a photodetector coupled between a first ground and the readout node;

a switching device selectively coupled to one of reset lines in the rows of pixels;

reference voltage source coupled between a second ground and one of the reset lines via the switching device, wherein the reference voltage source generates a reset voltage that is independent of the supply voltage and the first and second grounds have the same potential; and

an operational amplifier buffer comprising (1) an output coupled by the switching device to one of the reset lines, (2) a non-inverting input coupled to the reference voltage source to receive the reset voltage, and (3) an inverting input coupled to the output in a feedback loop, wherein the feedback loop does not pass through the readout node.

2. The image capture system of claim 1, wherein the first FET further comprises an n-channel enhancement mode MOSFET.

3. The image capture system of claim 1, wherein the ground referenced reset voltage is greater than the supply voltage.

4. The image capture system of claim 1, further comprising a second FET having a gate terminal coupled to the readout node and a drain terminal coupled to the supply voltage.

5. The image capture system of claim 4, further comprising a third FET having a gate terminal coupled to a row select line, a source terminal coupled to a column line, and a drain terminal coupled to a source terminal of the second FET.

6. The image capture system of claim 5, wherein the switching device comprises a multiplexer.