1T1R resistive memory array with chained structure

• US 7,298,640 B2
• Filed: 05/03/2005
• Issued: 11/20/2007
• Est. Priority Date: 05/03/2004
• Status: Active Grant

• Current Assignee: Symetrix Corporation, Panasonic Semiconductor Solutions Co., Ltd. (Winbond Electronics Corporation)
• Original Assignee: Matsushita Electric Industrial Company Limited (Panasonic Holdings Corporation), Symetrix Corporation
• Inventors: Paz de Araujo, Carlos A., McMillan, Larry D., Chen, Zheng
• Primary Examiner(s): Elms; Richard T.
• Assistant Examiner(s): Luu; Pho M.
• Application Number:
  US11/121,145
• Publication Number:
  US 20050248978A1
• Time in Patent Office: 931 Days
• Field of Search: 365/100, 365/104, 365/148, 365/189.04
• US Class Current: 365/148
• CPC Class Codes: G11C 11/16 using elements in which the storage effect is based on magnetic spin effect
• CPC Class Codes: G11C 13/0007 comprising metal oxide memory material, e.g. perovskites
• CPC Class Codes: G11C 13/003 Cell access
• CPC Class Codes: G11C 13/0069 Writing or programming circuits or methods
• CPC Class Codes: G11C 2013/009 Write using potential difference applied between cell electrodes
• CPC Class Codes: G11C 2213/31 Material having complex metal oxide, e.g. perovskite structure
• CPC Class Codes: G11C 2213/75 Array having a NAND structure comprising, for example, memory cells in series or memory elements in series, a memory element being a memory cell in parallel with an access transistor
• CPC Class Codes: G11C 2213/79 Array wherein the access device being a transistor
• CPC Class Codes: H10B 63/30 comprising selection components having three or more electrodes, e.g. transistors
• CPC Class Codes: H10B 63/80 Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays

Abstract

A 1T1R resistive memory array comprised of chains of memory cells, where each memory cell is composed of a resistive element in parallel with a switch. Such chains of memory cells are non-volatile and provide for each of the memory cells to be randomly accessed.

Claims

1. An electronic memory comprising a plurality of memory cells, each memory cell including:

a switch;

a resistive memory element connected in parallel with said switch, said resistive memory element capable of existing in one of a plurality of resistive states, each resistive state representing a different data state; and

a memory write and read circuit selectably coupled to said resistive memory element and capable of writing a data state to said resistive memory element and reading the data state;

wherein said plurality of memory cells are arranged in a row/column configuration, each row/column configuration including a plurality of said resistive memory elements connected in series and a plurality of said switches connected in series, each of said switches associated with one of said resistive memory elements; and

said memory further comprising a source of a programming voltage and a row/column selection transistor connected between said source of the programming voltage and said row/column of memory cells.

2. The electronic memory according to claim 1, further comprising a sense amplifier and a row/column sense transistor connected between said sense amplifier and said row/column of memory cells.

3. The electronic memory according to claim 1, wherein said resistive memory element includes a material selected from the group consisting of colossal magnetoresistance (CMR) materials and high temperature superconductivity (HTSC) materials.

4. The electronic memory according to claim 1, wherein said resistive memory element is composed of Pr_0.7Ca_0.3MnO₃.

5. The electronic memory according to claim 1, wherein each of said memory cells has a maximum size of 4F₂.