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Dual-mode decoder circuit, integrated circuit memory array incorporating same, and related methods of operation

  • US 7,298,665 B2
  • Filed: 12/30/2004
  • Issued: 11/20/2007
  • Est. Priority Date: 12/30/2004
  • Status: Active Grant
First Claim
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1. An integrated circuit comprising:

  • a memory array having a first plurality of decoded lines traversing across the memory array in a first direction;

    a pair of decoder circuits, one decoder circuit coupled to each of the plurality of decoded lines at one respective location along said decoded lines, and the other decoder circuit coupled to each of the plurality of decoded lines at another respective location along said decoded lines, both decoder circuits coupled to receive like address information.

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