Memory flash card reader employing an indexing scheme

• US 7,299,316 B2
• Filed: 10/01/2004
• Issued: 11/20/2007
• Est. Priority Date: 02/26/2004
• Status: Expired due to Fees

• Current Assignee: Super Talent Electronics, Inc.
• Original Assignee: Super Talent Electronics, Inc.
• Inventors: Lee, Edward W., Chou, Horng-Yee
• Primary Examiner(s): KIM, HONG CHONG
• Application Number:
  US10/956,826
• Publication Number:
  US 20050193162A1
• Time in Patent Office: 1,145 Days
• Field of Search: 711/103, 711/115, 711/159, 711/170, 711/109, 710/305
• US Class Current: 711/103
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 2212/7205 Cleaning, compaction, garbage collection, erase control
• CPC Class Codes: G06F 2212/7208 Multiple device management, e.g. distributing data over multiple flash devices

Abstract

A memory flash card reader includes a processor for receiving at least one request from a host system, an index comprising information regarding sectors of the memory flash card wherein the processor may utilize the index to determine sectors of the memory flash card that are available for programming, reprogramming, or reading, and at least one card controller coupled to the processor.

Claims

1. A memory flash card reader for writing to and reading from a memory flash card comprising:

a processor for receiving at least one request from a host system;

an index comprising information regarding sectors of the memory flash card wherein the processor may utilize the index to determine sectors of the memory flash card that are available for writing, erasing and reading, the index further comprising a write look up, table, a read look up table and a physical usage table;

a block copy and recycling first-in-first-out unit (FIFO); and

at least one card controller coupled to the processor.

2. The memory flash card reader of claim 1, wherein the at least one request comprises a logical block address for reading or writing and wherein the index maps the logical block address to a physical block address in the memory flash card.

3. The memory flash card reader of claim 1, wherein the processor is operable to recycle obsolete blocks from the FIFO in the background with respect to the host system to free up resources of the host system.

4. The memory flash card reader of claim 1, wherein the processor is operable to recycle obsolete blocks from the FIFO after a block sector copy process.

5. The memory flash card reader of claim 1, further comprising a Universal Serial Bus interface to the host system.

6. The memory flash card reader of claim 1, wherein the processor is operable to communicate with the host system using a Bulk Only Transport protocol.

7. The memory flash card reader of claim 1, wherein the processor is operable to communicate with the host system using the SCSI transparent command set protocol.

8. The memory flash card reader of claim 1, wherein the processor is operable to communicate with the host system using the Reduced Block Command T10 Project 240-D protocol.

9. The memory flash card reader of claim 1, wherein the memory flash card functions as a floppy disk.

10. The memory flash card reader of claim 1, wherein the memory flash card reader can be applied to USB and ExpressCard plug and receptacle systems.

11. The memory flash card reader of claim 1, wherein the at least one card controller comprises a USB controller.

12. The memory flash card reader of claim 1, wherein the at least one card controller comprises a Secure Digital controller.

13. The memory flash card reader of claim 1, wherein the at least one card controller comprises a MultiMediaCard controller.

14. The memory flash card reader of claim 1, wherein the at least one card controller comprises a Memory Stick controller.

15. The memory flash card reader of claim 1, wherein the at least one card controller comprises a Compact Flash controller.

16. The flash memory card reader of claim 1, wherein the processor, index and at least one card controller are housed in a box coupled to the host system by a cable.

17. The flash memory card reader of claim 1, wherein the processor, index and at least one card controller are housed in the host system.

18. A method of managing a flash memory comprising the steps of:

receiving at least one request from a host system in a processor within a flash memory controller;

determining which sectors of the flash memory are available for writing, erasing and reading utilizing the processor and an index coupled to the processor, the index comprising a write look up table, a read look up table and a physical usage table;

recycling obsolete blocks copy and recycling first-in-first-out unit (FIFO) after a block sector copy process; and

writing, erasing and reading to a flash memory card through at least one card controller coupled to the processor.

19. The method of managing a flash memory of claim 18, wherein determining which sectors of the flash memory are available for writing, erasing and reading comprises mapping a logical block address provided in the at least one request from the host system to a physical block address in the flash memory card utilizing the index.

20. The method of managing a flash memory of claim 18, wherein the recycling of obsolete blocks occurs in the background with respect to the host system to free up resources of the host system.

21. The method of managing a flash memory of claim 18, wherein the recycling of obsolete blocks occurs after a block sector copy of valid data from sectors of a first block to sectors of a second block, the first block becoming an obsolete block, and wherein the sectors of the first block are erased.

22. The method of managing a flash memory of claim 18, wherein the flash memory controller is coupled to the host system by a Universal Serial Bus interface.

23. The method of managing a flash memory of claim 18, wherein the processor is operable to communicate with the host system using a Bulk Only Transport protocol.

24. The method of managing a flash memory of claim 18, wherein the processor is operable to communicate with the host system using the SCSI transparent command set protocol.

25. The method of managing a flash memory of claim 18, wherein the processor is operable to communicate with the host system using the Reduced Block Command T10 Project 240-D protocol.

26. The method of managing a flash memory of claim 18, wherein the memory flash card functions as a floppy disk.

27. The method of managing a flash memory of claim 18, wherein the memory flash card reader can be applied to USB and ExpressCard plug and receptacle systems.

28. The method of managing a flash memory of claim 18, wherein the at least one card controller comprises a USB controller.

29. The method of managing a flash memory of claim 18, wherein the at least one card controller comprises a Secure Digital controller.

30. The method of managing a flash memory of claim 18, wherein the at least one card controller comprises a MultiMediaCard controller.

31. The method of managing a flash memory of claim 18, wherein the at least one card controller comprises a Memory Stick controller.

32. The method of managing a flash memory of claim 18, wherein the at least one card controller comprises a Compact Flash controller.