Semiconductor device having reduced intra-level and inter-level capacitance

• US 7,301,107 B2
• Filed: 10/27/2003
• Issued: 11/27/2007
• Est. Priority Date: 05/20/2002
• Status: Expired due to Term

• Current Assignee: Bell Semiconductor, LLC (Hilco Inc. (d/b/a Hilco Global))
• Original Assignee: Agere Systems Incorporated (Broadcom, Inc.)
• Inventors: Merchant, Sailesh Mansinh, Karthikeyan, Subramanian
• Primary Examiner(s): Reichard; Dean A.
• Assistant Examiner(s): NGUYEN, HOA CAO
• Application Number:
  US10/694,611
• Publication Number:
  US 20040084761A1
• Time in Patent Office: 1,492 Days
• Field of Search: 174/258, 174/262, 257/700, 257/702, 257/698
• US Class Current: 174/262
• CPC Class Codes: H01L 21/565 Moulds
• CPC Class Codes: H01L 21/76807 for dual damascene structures
• CPC Class Codes: H01L 21/76832 Multiple layers
• CPC Class Codes: H01L 21/76834 formation of thin insulating films on the sidewalls or on top of conductors H01L21/76831 takes precedence
• CPC Class Codes: H01L 21/76835 Combinations of two or more different dielectric layers having a low dielectric constant H01L21/76832 takes precedence
• CPC Class Codes: H01L 23/49575 Assemblies of semiconductor devices on lead frames
• CPC Class Codes: H01L 23/5222 Capacitive arrangements or effects of, or between wiring layers other capacitive arrangements H01L23/642
• CPC Class Codes: H01L 23/53295 Stacked insulating layers
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

An interconnect structure of a semiconductor device designed for reduced intralevel and interlevel capacitance, and includes a lower metal layer and an upper metal layer and an insulating layer interposed between metal layers. Each of the lower metal layer and upper metal layer include a plurality of conductive lines spaced apart and extending within a low-k dielectric material. A plurality of metal-filled vias interconnects the conductive lines of the lower metal layer to the conductive lines of the upper metal layer. The insulating layer comprises also comprises a low-k dielectric material disposed between the adjacent metal-filled vias. Openings, having been etched in the low-k dielectric material between the conductive lines of the upper and lower metal layers, and the metal-filled vias, an ultra-low k material is deposited within the openings. The integration of the ultra-low k and low-d dielectric materials reduces the overall capacitance of the structure to enhance performance.

Claims

1. A semiconductor device having an interconnect structure comprising:

a. a lower metal layer comprising a low-k dielectric material and a plurality of conductive lines disposed within said low-k dielectric material;

b. an upper metal layer comprising a low-k dielectric material and a plurality of conductive lines disposed within said low-k dielectric material;

c. an insulating layer, disposed between the lower metal layer and the upper metal layer, and comprising a low-k dielectric material;

d. a plurality of metal-filled vias extending through the insulating layer and interconnecting the conductive lines of the lower metal layer to the conductive lines of the upper metal layer;

e. a porous ultra low-k dielectric material regions disposed within the low-k dielectric material of the upper metal layer and the lower metal layer between adjacent conductive lines, and within the low-k dielectric material in the insulating layer;

f. a first barrier layer interposed between the lower metal layer and the insulating layer, said first barrier layer separating the ultra low-k material regions of the lower metal layer from the ultra low-k material regions of the insulating layer; and

g. a second barrier layer disposed over the upper metal layer, wherein said first barrier layer and said second barrier layer each have a first film and a second film disposed over the first film, wherein said first film covers the conductive lines and said porous ultra low-k dielectric material regions extend through said first film to said second film, which covers said ultra low-k dielectric material regions.

2. The semiconductor device of claim 1 wherein said porous ultra low-k dielectric material regions are formed in a plurality of ultra low-k dielectric-filled openings, each said dielectric-filled opening disposed within the low-k dielectric material between the metal lines in the upper metal layer and the lower metal layer.

3. The semiconductor device of claim 2 wherein said porous ultra low-k dielectric filled openings include openings extending from the upper metal layer to a predetermined depth of the insulating layer, which opening extend between the metal lines in the upper metal layer and the metal filled vias in the insulating layer.

4. The semiconductor device of claim 1 wherein said porous ultra low-k dielectric material regions include a plurality of ultra-low k dielectric columns, spaced apart and disposed within the low-k dielectric material of at least one of the layers including the lower metal layer, upper metal layer and the insulating layer.

5. The semiconductor device of claim 1 wherein the lines predominantly comprise copper.

6. The semiconductor device of claim 1 wherein the upper surface of the porous ultra low-k

dielectric regions are substantially planar.

7. The semiconductor device of claim 1 wherein one of the porous ultra low-k dielectric regions is formed over another of the porous ultra low-k dielectric regions.

8. The semiconductor device of claim 1 wherein the porous ultra low-k dielectric material regions extend through at least the low-k dielectric material of the insulating layer and the low-k dielectric material of the upper metal layer.