Electrostatic discharge (ESD) protection for integrated circuit packages

• US 7,301,229 B2
• Filed: 06/25/2004
• Issued: 11/27/2007
• Est. Priority Date: 06/25/2004
• Status: Expired due to Fees

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Yau, Sin-Him
• Primary Examiner(s): NGO, NGAN V
• Application Number:
  US10/876,980
• Publication Number:
  US 20050285280A1
• Time in Patent Office: 1,250 Days
• Field of Search: 257/700, 257/762, 257/773
• US Class Current: 257/700
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/05553 being rectangular
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/451 with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
• CPC Class Codes: H01L 2224/48247 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/4912 Layout
• CPC Class Codes: H01L 2224/49171 Fan-out arrangements
• CPC Class Codes: H01L 23/49541 Geometry of the lead-frame
• CPC Class Codes: H01L 23/49816 Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
• CPC Class Codes: H01L 23/60 Protection against electrostatic charges or discharges, e.g. Faraday shields
• CPC Class Codes: H01L 24/06 of a plurality of bonding areas
• CPC Class Codes: H01L 24/45 of an individual wire connector
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 24/49 of a plurality of wire connectors
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01013 Aluminum [Al]
• CPC Class Codes: H01L 2924/01014 Silicon [Si]
• CPC Class Codes: H01L 2924/01023 Vanadium [V]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/14 : Integrated circuits

Abstract

An integrated circuit package includes a package substrate with a plurality of pins coupled to a semiconductor chip having a plurality of bond pads, some of which are ic bond pads coupled to an integrated circuit formed on the semiconductor chip and others of which are floating bond pads that are isolated from the integrated circuit. The plurality of pins include active pins coupled to active bond pads and dummy (non-coupled) pins coupled to floating bond pads. The floating bond pads are formed of interconnect materials also used to form the integrated circuit. BGA or flip-chip IC packages may be used and a method is provided for forming the IC package. The floating bond bad design prevents ESD (electrostatic discharge) from damaging the active device due to an adjacent non-coupled pin of the package being subjected to ESD.

Claims

1. An assembly comprising a package substrate having a plurality of pins and coupled to a semiconductor chip, each of said plurality of pins connected to one of:

an ic bond pad disposed on said semiconductor chip and coupled to an integrated circuit of said semiconductor chip; and

a floating bond pad disposed on said semiconductor chip and not conductively coupled to any further components on or in said semiconductor chip,

wherein said integrated circuit is formed of a plurality of metal layers and said floating bond pad includes a discrete portion of each of said metal layers, each discrete portion isolated from other portions of said respective metal layer and said respective discrete portions aligned over and contacting one another.

2. The assembly as in claim 1, wherein said semiconductor chip includes a silicon substrate.

3. The assembly as in claim 1, wherein said package substrate is a metal lead frame and said plurality of pins substantially surround said semiconductor chip.

4. The assembly as in claim 1, wherein said package substrate is a BGA substrate and each of said plurality of pins is wire bonded to said one of an ic bond pad and a floating bond pad.

5. The assembly as in claim 1, wherein said assembly is resistant to damage due to ESD discharge when an HBM ESD stress of up to 4 kV, is applied to any of said plurality of pins.

13. The assembly as in claim 1, wherein said semiconductor chip includes a silicon substrate and each of said plurality of metal layers comprise one of copper, aluminum or alloys thereof.

14. The assembly as in claim 1, wherein said plurality of metal layers include at least one copper layer.

6. An assembly comprising a package substrate having a plurality of contacts and coupled to a semiconductor chip, each of said plurality of contacts connected to one of:

an ic bond pad disposed on said semiconductor chip and coupled to an integrated circuit of said semiconductor chip; and

a floating bond pad disposed on said semiconductor chip and not conductively coupled to an active component on or in said semiconductor chip,

wherein said integrated circuit is formed of a plurality of metal layers and said floating bond pad includes a discrete portion of each of said metal layers, each discrete portion isolated from other portions of said respective metal layer and said respective discrete portions contacting one another but misaligned with respect to one another.

7. The assembly as in claim 6, wherein each of said plurality of contacts is joined to said one of an ic bond pad and a floating bond pad using flip chip mounting techniques and further comprising solder disposed between each of said plurality of contacts and said one of an ic bond pad and a floating bond pad.

12. The assembly as in claim 6, wherein said package substrate is a BGA substrate, each of said plurality of pins is wire bonded to said one of an ic bond pad and a floating bond pad, and said assembly is resistant to damage due to ESD discharge when an HBM ESD stress of up to 4 kV is applied to any of said plurality of contacts.

8. An assembly comprising a package substrate having a plurality of contacts and coupled to a semiconductor chip including an integrated circuit, said plurality of contacts including a plurality of active contacts that are each coupled to an ic bond pad coupled to said integrated circuit, and at least one dummy contact connected to a floating bond pad disposed on said semiconductor chip and not conductively coupled to any further components on or in said semiconductor chip,

wherein said integrated circuit is formed of a plurality of metal layers and said floating bond pad includes a discrete portion of each of said metal layers, each discrete portion isolated from other portions of said respective metal layer and said respective discrete portions aligned over and contacting one another.

9. The assembly as in claim 8, wherein said package substrate is a BGA substrate and each of said plurality of active contacts is a pin wire bonded to one of said ic bond pads and each of said at least one dummy contact is a dummy pin wire bonded to said floating bond pad.

10. The assembly as in claim 8, wherein said package substrate is a flip chip and each of said plurality of active contacts is flip chip soldered to one of said ic bond pads and each of said at least one dummy contact is flip chip soldered to said floating bond pad.

11. The assembly as in claim 8, wherein said package substrate is a flip chip and each of said plurality of active contacts is flip chip soldered to one of said ic bond pads and each of said at least one dummy contact is flip chip soldered to said floating bond pad.