Duplicated double checking production rule set for fault-tolerant electronics

• US 7,301,362 B2
• Filed: 03/14/2006
• Issued: 11/27/2007
• Est. Priority Date: 03/14/2005
• Status: Expired due to Fees

• Current Assignee: California Institute of Technology
• Original Assignee: California Institute of Technology
• Inventors: Martin, Alain J., Jang, Wonjin, Nystroem, Mika, Dama, Jonathan A.
• Primary Examiner(s): Tran; Anh Q.
• Application Number:
  US11/375,390
• Publication Number:
  US 20070016823A1
• Time in Patent Office: 623 Days
• Field of Search: 326 9- 10, 326 14- 15, 326 93- 94, 326/112, 326/119
• US Class Current: 326/9
• CPC Class Codes: H03K 19/0075 by using two redundant chains

Abstract

Systems and methods for mitigating the effects of soft errors in asynchronous digital circuits. Circuits are constructed using stages comprising doubled logic elements which are connected to c-elements that compare the output states of the double logic elements. The inputs of logic elements in a stage are inhibited from changing until the outputs of the c-elements of that stage are enabled. The c-elements inhibit the propagation of a soft error by halting the operation of the circuit until the temporary effects of the soft error pass.

Claims

1. A method of mitigating soft errors in an asynchronous digital circuit having a stage comprising duplicate asynchronous circuit elements, each of said duplicate asynchronous digital circuit elements having at least one input terminal and at least one output terminal, each of said duplicate asynchronous digital circuit elements providing the same logic operation, comprising the steps of:

(a) asserting a digital signal at corresponding ones of each of said at least one input terminals of said duplicate asynchronous digital circuit elements;

(b) inhibiting a variation of said asserted digital signal asserted at corresponding ones of each of said at least one input terminals of said duplicate asynchronous digital circuit elements;

(c) comparing an output signal appearing at said at least one output terminal of one of said duplicate asynchronous digital circuit elements with a corresponding output signal appearing at said at least one output terminal of the other of said duplicate asynchronous digital circuit elements; and

based on the result of the comparison of the output signals;

(d) if said output signals are not deemed equivalent;

(1) inhibiting a resultant signal from being provided as output from the stage;

(2) maintaining the step of inhibiting a variation of said asserted digital signal asserted at corresponding ones of each of said at least one input terminals of said duplicate asynchronous digital circuit elements;

(3) continuing to compare an output signal appearing at said at least one output terminal of one of said duplicate asynchronous digital circuit elements with a corresponding output signal appearing at said at least one output terminal of the other of said duplicate asynchronous digital circuit elements; and

(4) continuing steps (d)(1), (d)(2) and (d)(3) until said output signals are deemed equivalent; and

(e) if said output signals are deemed equivalent;

(1) providing at least one resultant signal as output from the stage; and

(2) permitting a variation of the asserted digital signal asserted at corresponding ones of each of said at least one input terminals of said duplicate

asynchronous digital circuit elements;

whereby the stage comprising duplicate asynchronous digital circuit elements is active in the absence of soft errors and is prevented from being active during the presence of soft errors, thereby eliminating soft errors from propagating in the asynchronous digital circuit.

2. The method of mitigating soft errors in an asynchronous digital circuit having a stage comprising duplicate asynchronous circuit elements of claim 1, wherein said method employs three or more stages comprising duplicate asynchronous circuit elements.

3. The method of mitigating soft errors in an asynchronous digital circuit having a stage comprising duplicate asynchronous circuit elements of claim 1, wherein the step of comparing an output signal appearing at said at least one output terminal of one of said duplicate asynchronous digital circuit elements with a corresponding output signal appearing at said at least one output terminal of the other of said duplicate asynchronous digital circuit elements is performed by a c-element.

4. The method of mitigating soft errors in an asynchronous digital circuit having a stage comprising duplicate asynchronous circuit elements of claim 1, wherein the step of inhibiting a variation of said asserted digital signal asserted at corresponding ones of each of said at least one input terminals of said duplicate asynchronous digital circuit elements is performed by a c-element.

5. The method of mitigating soft errors in an asynchronous digital circuit having a stage comprising duplicate asynchronous circuit elements of claim 1, wherein the step of inhibiting a resultant signal from being provided as output from the stage is performed by a c-element.

6. The method of mitigating soft errors in an asynchronous digital circuit having a stage comprising duplicate asynchronous circuit elements of claim 1, wherein said method corrects a plurality of soft errors using a weak c-element.

7. An asynchronous digital circuit configured to mitigate soft error propagation, comprising:

a stage comprising duplicate asynchronous circuit elements, each of said duplicate asynchronous digital circuit elements having at least one input terminal and at least one output terminal, each of said duplicate asynchronous digital circuit elements providing the same logic operation;

a first comparison element having two input terminals and a first output, a selected one of said two input terminals connected to each of said at least one output terminal of each of said duplicate asynchronous digital circuit elements, and a second comparison element having two input terminals and a second output, a selected one of said two input terminals connected to each of said at least one output terminal of each of said duplicate asynchronous digital circuit elements; and

a control element in electrical communication with said first output of said first comparison element and said second output of said second comparison element, said control element configured to provide control signals based on the equivalence or lack of equivalence of signals appearing at said first output of said first comparison element and said second output of said second comparison element;

in the event that the signals appearing at said first and second outputs are not equivalent;

said control element provides a control signal to inhibit a resultant signal from appearing as output at an output terminal of the stage; and

said control element provides a control signal to inhibit a variation of said asserted digital signal asserted at corresponding ones of each of said at least one input terminals of said duplicate asynchronous digital circuit elements; and

in the event that the signals appearing at said first and second outputs are equivalent;

said control element provides a control signal to allow at least one resultant signal as output at said output terminal the stage; and

said control element provides a control signal to permit a variation of the asserted digital signal asserted at corresponding ones of each of said at least one input terminals of said duplicate asynchronous digital circuit elements;

so that the stage comprising duplicate asynchronous digital circuit elements is active to provide a signal representing said logic operation in the absence of soft errors and is prevented from being active during the presence of soft errors, thereby eliminating soft errors from propagating in the asynchronous digital circuit.

8. The asynchronous digital circuit configured to mitigate soft error propagation of claim 7, wherein said asynchronous digital circuit comprises three or more stages comprising duplicate asynchronous circuit elements.

9. The asynchronous digital circuit configured to mitigate soft error propagation of claim 7, wherein said first comparison element is a c-element.

10. The asynchronous digital circuit configured to mitigate soft error propagation of claim 7, wherein said control element is combined with said comparison element.

11. The asynchronous digital circuit configured to mitigate soft error propagation of claim 7, wherein said circuit is a field programmable gate array.

12. The asynchronous digital circuit configured to mitigate soft error propagation of claim 7, wherein said circuit comprises dual interlocked programmable bits.

13. The asynchronous digital circuit configured to mitigate soft error propagation of claim 7, wherein said circuit comprises a pre-charged half buffer.

14. The asynchronous digital circuit configured to mitigate soft error propagation of claim 7, wherein said circuit comprises a weak c-element.