Embedding memory within tile arrangement of a configurable IC

• US 7,301,368 B2
• Filed: 03/15/2005
• Issued: 11/27/2007
• Est. Priority Date: 03/15/2005
• Status: Expired due to Fees

• Current Assignee: Altera Corporation (Intel Corporation)
• Original Assignee: Tabula Incorporated
• Inventors: Schmit, Herman, Redgrave, Jason
• Primary Examiner(s): Tan, Vibol
• Application Number:
  US11/081,867
• Publication Number:
  US 20070241772A1
• Time in Patent Office: 987 Days
• Field of Search: 326/39, 326/41
• US Class Current: 326/38
• CPC Class Codes: H01L 2224/32145 the bodies being stacked
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/15311 being a ball array, e.g. BGA
• CPC Class Codes: H03K 19/17728 Reconfigurable logic blocks, e.g. lookup tables
• CPC Class Codes: H03K 19/17736 Structural details of routing resources
• CPC Class Codes: H03K 19/1776 for memories

Abstract

Some embodiments of the invention provide a configurable IC that includes several configurable computational tiles and several memory tiles. Each computational tile has a set of configurable logic circuits for configurably performing a plurality of computations and a set of configurable routing circuits. The routing circuits of the tiles configurably route signals between configurable logic circuits. Each memory tiles includes a set of routing circuits and a memory array for storing data on which the logic circuit perform computation. In this IC, at least a first memory tile has the same set of configurable routing circuits as at least a second computational tile.

Claims

1. A configurable IC comprising:

a) a plurality of configurable computational tiles and a plurality of memory tiles;

b) each configurable computational tile comprising a set of configurable logic circuits for configurably performing a plurality of computations and a set of configurable routing circuits, said configurable routing circuits of said configurable computational tiles for configurably routing signals between configurable logic circuits;

c) each memory tile comprising a set of configurable routing circuits and at least one memory array for storing data that serve as variables in the computations of the configurable logic circuits;

d) wherein at least a first memory tile comprises the same set of configurable routing circuits as at least a second configurable computational tile.

2. The configurable IC of claim 1,

a) wherein each particular configurable computational tile includes a plurality of input select interconnects, each input select interconnect for receiving a plurality of signals and supplying a set of the received signals to a configurable logic circuit in the particular configurable computational tile;

b) wherein each particular memory tile includes a plurality of input select interconnects, each input select interconnect for receiving a plurality of signals and supplying a set of the received signals to the memory array in the particular memory tile;

c) wherein the first memory tile comprises the same set of input select interconnects as the second configurable computational tile.

3. The configurable IC of claim 2, wherein two sets of input select interconnects are the same when the two sets include the same number of input select interconnects and the input select interconnects receive the same number of signals.

4. The configurable IC of claim 3, wherein two sets of interconnects are the same when the relative positions of the interconnects of one set are the same as the relative positions of the interconnects of the other set.

5. The configurable IC of claim 2, wherein the configurable routing circuits within a particular tile connect to the input select interconnects within the particular tile and within other tiles.

6. The configurable IC of claim 5,

a) wherein the configurable routing circuits of the first memory tile have a first set of connections to the input select interconnects of the first memory tile;

b) wherein the configurable routing circuits of the second configurable computational tile have a second set of connections to the input select interconnects of the second configurable computational tile, wherein the first and second sets of connections are similar.

7. The configurable IC of claim 1, wherein two sets of configurable routing circuits are the same when the two sets include the same number of configurable routing circuits and the configurable routing circuits receive the same number of signals.

8. The configurable IC of claim 1, wherein two sets of configurable routing circuits are the same when the relative positions of the configurable routing circuits of one set are the same as the relative positions of the configurable routing circuits of the other set.

9. The configurable IC of claim 1, wherein the memory array occupies an area in the memory tile that corresponds to an area in the configurable computational tile occupied by the set of configurable logic circuits in the configurable computational tile.

10. The configurable IC of claim 1, wherein said configurable routing circuits form a routing network for routing signals between configurable logic circuits and between configurable logic circuits and memory arrays, wherein the memory arrays do not create a discontinuity in the routing network.

11. The configurable IC of claim 10, wherein the routing network in a section about the configurable IC that contains a memory array embedded in a memory tile is the same as the routing network in a section that does not contain the memory array.

12. An electronic device comprising:

a configurable IC comprising;

a plurality of configurable computational tiles and a plurality of memory tiles;

each configurable computational tile comprising a set of configurable logic circuits for configurably performing a plurality of computations and a set of configurable routing circuits, said configurable routing circuits of said configurable computational tiles for configurably routing signals between configurable logic circuits;

each memory tile comprising a set of configurable routing circuits and at least one memory array for storing data that serve as variables in the computations of the configurable logic circuits;

wherein at least a first memory tile comprises the same set of configurable routing circuits as at least a second configurable computational tile.

13. The electronic device of claim 12, wherein the configurable IC further comprises:

wherein each particular configurable computational tile includes a plurality of input select interconnects, each input select interconnect for receiving a plurality of signals and supplying a set of the received signals to a configurable logic circuit in the particular configurable computational tile;

wherein each particular memory tile includes a plurality of input select interconnects, each input select interconnect for receiving a plurality of signals and supplying a set of the received signals to the memory array in the particular memory tile;

wherein the first memory tile comprises the same set of input select interconnects as the second configurable computational tile.

14. The electronic device of claim 13, wherein two sets of input select interconnects are the same when the two sets include the same number of input select interconnects and the input select interconnects receive the same number of signals.

15. The electronic device of claim 14, wherein two sets of interconnects are the same when the relative positions of the interconnects of one set are the same as the relative positions of the interconnects of the other set.

16. The electronic device of claim 13, wherein the configurable routing circuits within a particular tile connect to the input select interconnects within the particular tile and within other tiles.

17. The electronic device of claim 16,

a) wherein the configurable routing circuits of the first memory tile have a first set of connections to the input select interconnects of the first memory tile;

b) wherein the configurable routing circuits of the second configurable computational tile have a second set of connections to the input select interconnects of the second configurable computational tile, wherein the first and second sets of connections are similar.

18. The electronic device of claim 12, wherein two sets of configurable routing circuits are the same when the two sets include the same number of configurable routing circuits and the configurable routing circuits receive the same number of signals.

19. The electronic device of claim 12, wherein two sets of configurable routing circuits are the same when the relative positions of the configurable routing circuits of one set are the same as the relative positions of the configurable routing circuits of the other set.

20. The electronic device of claim 12, wherein the memory array occupies the same location in the memory tile as the set of configurable logic circuits occupy in the configurable computational tile.

21. The electronic device of claim 12, wherein said configurable routing circuits form a routing network for routing signals between configurable logic circuits and between configurable logic circuits and memory arrays, wherein the memory arrays do not create a discontinuity in the routing network.

22. The electronic device of claim 21, wherein the routing network in a section about the configurable IC that contains a memory array embedded in a memory tile is the same as the routing network in a section that does not contain the memory array.