Digital PWM controller for preventing limit cycle oscillations

• US 7,301,488 B2
• Filed: 03/31/2005
• Issued: 11/27/2007
• Est. Priority Date: 03/31/2005
• Status: Expired due to Fees

• Current Assignee: Silicon Laboratories Incorporated
• Original Assignee: Silicon Laboratories Incorporated
• Inventors: Leung, Ka Y., Xiao, Jinwen
• Primary Examiner(s): Nguyen; Khai M.
• Application Number:
  US11/095,193
• Publication Number:
  US 20060227860A1
• Time in Patent Office: 971 Days
• Field of Search: 341/131
• US Class Current: 341/131
• CPC Class Codes: H02M 3/157 with digital control
• CPC Class Codes: H03K 7/08 Duration or width modulation ; Duty cycle modulation

Abstract

An apparatus and method for minimizing limit cycle oscillations within a switched power supply includes providing a programmable dither signal as an input to the digital control loop connected between an output and a control input of the switched power supply. The dither signal minimizes limit cycle oscillations from the output of the switched power supply.

Claims

1. A method for minimizing limit cycle oscillations from an output of a switched power supply including a digital control loop having a digital pulse width modulator therein with a digital control input, comprising the steps of:

combining a digital dither signal with a digital output of a digital proportional integral derivative engine in the digital control loop to provide a combined signal to drive the digital control input of the digital pulse width modulator, the digital dither signal comprising a noise signal; and

generating an output signal from the switched power supply based upon the combined signal, wherein limit cycle oscillations in the output signal appear as random noise in the output signal due to the digital dither signal.

2. The method of claim 1 further including the step of programmably selecting an amount of the dither signal.

3. The method of claim 1, wherein the step of combining further comprises the steps of:

providing the dither signal to the output of the proportional integral derivative engine; and

adding the dither signal to the output of the proportional integral derivative engine.

4. The method of claim 1, wherein the dither signal does not introduce noise at DC into an output of the switched power supply.

5. The method of claim 1, wherein the dither signal causes limit cycle oscillations to appear as random noise within the output rather than as a periodic signal.

6. A method for minimizing limit cycle oscillations from an output of a switched power supply including a digital control loop having a digital pulse width modulator therein, comprising the steps of:

combining a dither signal with an output of a proportional integral derivative engine in the digital control loop to provide a combined signal;

generating an output signal with minimized limit cycle oscillations from the switched power supply based upon the combined signal; and

programmably selecting a resolution of an LSB of a programmable analog to digital converter in the digital control loop, wherein the programmably selected resolution of the LSB is greater than a LSB resolution of the digital pulse width modulator.

7. The method of claim 6, wherein the step of generating further comprises the step of generating the output signal with minimized limit cycle oscillations from the switched power supply based upon the combined signal and the programmably selected LSB resolution of the analog to digital converter.

8. A method for minimizing limit cycle oscillations from an output of a switched power supply including a digital control loop having a digital pulse width modulator therein, comprising the steps of:

programmably selecting a resolution of an LSB of a programmable analog to digital converter in the digital control loop, wherein the programmably selected resolution of the LSB is greater than a LSB resolution of the digital pulse width modulator;

combining a dither signal with the output of a proportional integral derivative engine in the digital control loop to provide a combined signal; and

generating the output signal with minimized limit cycle oscillations from the switched power supply based upon the combined signal and the programmably selected LSB resolution of the analog to digital converter.

9. The method of claim 8 further including the step of programmably selecting an amount of the dither signal.

10. The method of claim 8, wherein the step of combining further comprises the steps of:

providing the dither signal to the output of the proportional integral derivative engine; and

adding the dither signal to the output of the proportional integral derivative engine.

11. The method of claim 8, wherein the dither signal does not introduce noise into an output of the switched power supply.

12. An apparatus, comprising:

a switched power supply having an input, an output and a control input;

a digital control loop connected between the output and the control input, the digital control loop having an analog input and a digital input; and

a digital input to the digital control loop for receiving a digital dither signal, the digital dither signal comprising a noise signal for causing limit cycle oscillations to appear as random noise in an output signal of the switched power supply.

13. The apparatus of claim 12, wherein the dither signal is programmable via an associated controller.

14. The apparatus of claim 12, wherein the dither signal does not introduce noise into an output of the switched power supply.

15. The apparatus of claim 12 wherein the dither signal is independent of the output of the switched power supply.

16. The apparatus of claim 12 wherein the dither signal is continuously combined with the digital output of the digital proportional integral derivative engine.

17. An apparatus, comprising:

a switched power supply having an input, an output and a control input;

a digital control loop connected between the output and the control input; and

an input to the digital control loop for a dither signal, the dither signal comprising a noise signal causing limit cycle oscillations to appear as random noise in an output signal of the switched power supply, wherein the digital control loop further comprises;

an analog to digital converter connected to the output of the switched power supply;

a proportional integral derivative engine connected to the analog to digital converter;

an adder circuit connected to an output of the proportional integral derivative engine and the input to the digital control loop for combining the dither signal with the output of the proportional integral derivative engine to provide a combined signal that causes limit cycle oscillations to appear as random noise in the output signal; and

a digital pulse width modulator for generating the output signal to control the switched power supply.

18. The apparatus of claim 17, wherein a resolution of an LSB of the analog to digital converter in the digital control loop is programmably selectable.

19. The apparatus of claim 18, wherein the programmably selected resolution of the LSB of the analog to digital converter is greater than an LSB resolution of the digital pulse width modulator.

20. The apparatus of claim 17, wherein the switched power supply generates the output signal with minimized limit cycle oscillations based upon the combined signal and the programmably selected LSB resolution of the analog to digital converter.

21. A digital control loop for a switched power supply, comprising:

an analog to digital converter connected to an output of the switched power supply;

a proportional integral derivative engine connected to the analog to digital converter;

an input to the digital control loop for a dither signal, the dither signal comprising a noise signal for causing limit cycle oscillations to appear as random noise in an output signal of the switched power supply;

an adder circuit connected to an output of the proportional integral derivative engine and to the input to the control loop for combining the dither signal with the output of the proportional integral derivative engine in the digital control loop to provide a combined signal; and

a digital pulse width modulator for generating the output signal for controlling the switched power supply based upon the combined signal.

22. The apparatus of claim 21, wherein a resolution of an LSB of the analog to digital converter in the digital control loop is programmably selectable.

23. The apparatus of claim 22, wherein the programmably selected resolution of the LSB is greater than an LSB resolution of the digital pulse width modulator.

24. The apparatus of claim 21, wherein the dither signal is programmable via an associated controller.

25. The apparatus of claim 21, wherein the dither signal causes limit cycle oscillations to appear as random noise within the output rather than as a periodic signal.