Bipolar reading technique for a memory cell having an electrically floating body transistor

• US 7,301,803 B2
• Filed: 12/15/2005
• Issued: 11/27/2007
• Est. Priority Date: 12/22/2004
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Innovative Silicon, S.A.
• Inventors: Okhonin, Serguei, Nagoga, Mikhail
• Primary Examiner(s): LE, THONG QUOC
• Application Number:
  US11/304,387
• Publication Number:
  US 20060131650A1
• Time in Patent Office: 712 Days
• Field of Search: 365/177, 365/191, 365/189.04, 365/189.01
• US Class Current: 365/177
• CPC Class Codes: G11C 11/404 with one charge-transfer gate, e.g. MOS transistor, per cell
• CPC Class Codes: G11C 11/4076 Timing circuits for regeneration management G11C11/406
• CPC Class Codes: G11C 2211/4016 Memory devices with silicon-on-insulator cells
• CPC Class Codes: H01L 29/78 with field effect produced by an insulated gate H01L29/7725, H01L29/775, H01L29/778 take precedence
• CPC Class Codes: H01L 29/7841 with floating body, e.g. programmable transistors
• CPC Class Codes: H10B 12/00 Dynamic random access memory [DRAM] devices
• CPC Class Codes: H10B 12/10 DRAM devices comprising bipolar components

Abstract

A method and a device for the coding and decoding of an information symbol for transmission over a transmission channel or a received signal value is described and illustrated, whereby a channel symbol used for coding is selected from at least two available channel symbols by means of a pre-calculated expected received signal value. The pre-calculation is achieved, based on the echo properties of the transmission channel and transmission values already sent. A pre-coding method with low receiver-side calculation requirement is thus prepared, whereby the information symbol can be transmitted by means of various channel symbols and thus various transmission values can also be transmitted. The possible selections may be used for minimization of the transmission energy and/or to achieve a minimal disturbance or even a constructive effect through the inter-symbol interference occurring on transmission.

Claims

1. An integrated circuit device comprising:

a memory cell consisting essentially of an electrically floating body transistor, wherein the electrically floating body transistor comprises;

a source region;

a drain region;

a body region disposed between the source region and the drain region,

wherein the body region is electrically floating; and

a gate disposed over the body region; and

wherein the memory cell includes (i) a first data state which is representative of a first charge in the body region of the electrically floating body transistor, and (ii) a second data state which is representative of a second charge in the body region of the electrically floating body transistor;

data writing circuitry, coupled to the memory cell, to write a data state into the memory cell; and

data sensing circuitry, coupled to the memory cell, to sense the data state of the memory cell;

wherein, in response to write control signals applied to the electrically floating body transistor, the electrically floating body transistor stores a charge which is representative of the data state of the memory cell in the body region of the electrically floating body transistor; and

wherein, in response to read control signals applied to the electrically floating body transistor, the electrically floating body transistor generates a bipolar transistor current which is representative of the data state of the memory cell and wherein the data sensing circuitry determines the data state of the memory cell substantially based on the bipolar transistor current of the electrically floating body transistor.

2. The integrated circuit device of claim 1 wherein electrically floating body transistor is an N-channel type transistor.

3. The integrated circuit device of claim 1 wherein electrically floating body transistor is a P-channel type transistor.

4. The integrated circuit device of claim 1 wherein the read control signals include a signal applied to the gate, source region, and drain region to cause, force and/or induce the bipolar transistor current which is representative of the data state of the memory cell.

5. The integrated circuit device of claim 4 wherein the read control signals include a positive voltage pulse which is applied to the drain region of the electrically floating body transistor and wherein the data sensing circuitry is connected to the drain region via a bit line.

6. The integrated circuit device of claim 4 wherein the read control signals include a negative voltage pulse which is applied to the drain region of the electrically floating body transistor and wherein the data sensing circuitry is connected to the drain region via a bit line.

7. The integrated circuit device of claim 1 wherein the electrically floating body transistor is non-symmetrical.

8. An integrated circuit device comprising:

a memory cell consisting essentially of an electrically floating body transistor, wherein the electrically floating body transistor consists, essentially of;

a first region having impurities to provide a first conductivity type;

a second region having impurities to provide the first conductivity type;

a body region disposed between the first region and the second region wherein the body region is electrically floating and includes impurities to provide a second conductivity type wherein the second conductivity type is different from the first conductivity type;

a gate disposed over the body region;

wherein each the memory cell includes (i) a first data state which is representative of a first charge in the body region of the transistor, and (ii) a second data state which is representative of a second charge in the body region of the transistor;

data writing circuitry, coupled to the memory cell, to write a data state into the memory cell; and

data sensing circuitry, coupled to the memory cell, to sense the data state of the memory cell;

memory cell control circuitry, coupled to the memory cell, to generate and apply read control signals and write control signals to the electrically floating body transistor;

wherein, in response to the write control signals applied to the electrically floating body transistor, the electrically floating body transistor stores a charge which is representative of the data state of the memory cell in the body region of the electrically floating body transistor; and

wherein, in response to the read control signals, the electrically floating body transistor generates a bipolar transistor current which is representative of the data state of the memory cell and wherein the data sensing circuitry determines the data state of the memory cell substantially based on the bipolar transistor current of the electrically floating body transistor.

9. The integrated circuit device of claim 8 wherein electrically floating body transistor is an N-channel type transistor.

10. The integrated circuit device of claim 8 wherein electrically floating body transistor is a P-channel type transistor.

11. The integrated circuit device of claim 8 wherein the read control signals include a signal applied to the gate, first region, and second region to cause, force and/or induce the bipolar transistor current which is representative of the data state of the memory cell.

12. The integrated circuit device of claim 10 wherein the read control signals include a positive voltage pulse which is applied to the second region of the electrically floating body transistor and wherein the data sensing circuitry is connected to the second region via a bit line.

13. The integrated circuit device of claim 11 wherein the read control signals include a negative voltage pulse which is applied to the second region of the electrically floating body transistor and wherein the data sensing circuitry is connected to the second region via a bit line.

14. The integrated circuit device of claim 8 wherein the electrically floating body transistor is non-symmetrical.

15. An integrated circuit device comprising:

a memory cell consisting of an electrically floating body transistor, wherein the electrically floating body transistor disposed in or on a semiconductor region or layer which resides on or above an insulating region or layer of a substrate, the electrically floating body transistor includes;

a source region having impurities to provide a first conductivity type;

a drain region having impurities to provide the first conductivity type,

a body region disposed between the source region, the drain region and the insulating region or layer of the substrate, wherein the body region is electrically floating and includes impurities to provide a second conductivity type wherein the second conductivity type is different from the first conductivity type;

a gate spaced apart from the body region;

wherein the memory cell includes (i) a first data state which is representative of a first charge in the body region of the transistor, and (ii) a second data state which is representative of a second charge in the body region of the transistor;

data sensing circuitry, coupled to the memory cell, to sense the data state of the memory cell;

memory cell control circuitry, coupled to the memory cell, to generate and apply read control signals and write control signals to the electrically floating body transistor;

wherein, in response to the write control signals applied to the electrically floating body transistor, the electrically floating body transistor stores a charge which is representative of the data state of the memory cell in the body region of the electrically floating body transistor; and

wherein, in response to the read control signals, the electrically floating body transistor generates a bipolar transistor current which is representative of the data state of the memory cell and wherein the data sensing circuitry determines the data state of the memory cell substantially based on the bipolar transistor current of the electrically floating body transistor.

16. The integrated circuit device of claim 15 wherein electrically floating body transistor is an N-channel type transistor.

17. The integrated circuit device of claim 15 wherein electrically floating body transistor is a P-channel type transistor.

18. The integrated circuit device of claim 15 wherein the read control signals include a signal applied to the gate, source region, and drain region to cause, force and/or induce the bipolar transistor current which is representative of the data state of the memory cell.

19. The integrated circuit device of claim 18 wherein the read control signals include a positive voltage pulse which is applied to the drain region of the electrically floating body transistor and wherein the data sensing circuitry is connected to the drain region via a bit line.

20. The integrated circuit device of claim 18 wherein the read control signals include a negative voltage pulse which is applied to the drain region of the electrically floating body transistor and wherein the data sensing circuitry is connected to the drain region via a bit line.

21. The integrated circuit device of claim 15 wherein the electrically floating body transistor is non-symmetrical.