Method and apparatus for communication within an integrated circuit

• US 7,301,824 B1
• Filed: 10/04/2005
• Issued: 11/27/2007
• Est. Priority Date: 10/04/2005
• Status: Active Grant

• Current Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Original Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Inventors: New, Bernard J.
• Primary Examiner(s): Tan; Vibol
• Application Number:
  US11/243,774
• Time in Patent Office: 784 Days
• Field of Search: 326/38, 326/39, 365/189.01, 365/189.02, 365/230.02, 365/236
• US Class Current: 365/189.011
• CPC Class Codes: G11C 5/063 Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay
• CPC Class Codes: G11C 8/16 Multiple access memory array, e.g. addressing one storage element via at least two independent addressing line groups

Abstract

Method and apparatus for communication within an integrated circuit is described. In one example, an integrated circuit includes a first logic circuit, a second logic circuit, first first-in-first-out (FIFO) logic, second FIFO logic, and an interconnection network. Each of the first FIFO logic and the second FIFO logic is configured for asynchronous serial communication over the interconnection network. Each of the first FIFO logic and the second FIFO logic is further configured to respectively communicate with each of the first logic circuit and the second logic circuit in respective synchronous time domains.

Claims

1. Apparatus for communication, comprising:

an integrated circuit including a first logic circuit, a second logic circuit, first first-in-first-out (FIFO) logic, second FIFO logic, and an interconnection network;

wherein said first FIFO logic and said second FIFO logic each comprise;

a dual-port memory having a write port and a read port;

an asynchronous receiver in communication with said write port;

an asynchronous driver in communication with said read port; and

a multiplexer having a first input port in communication with said asynchronous receiver, a second input port in communication with a respective one of said first logic circuit and said second logic circuit, and an output port in communication with said write port;

wherein said first FIFO logic and said second FIFO logic are configured for asynchronous serial communication over said interconnection network; and

said first FIFO logic and said second FIFO logic are configured to respectively communicate with each said first logic circuit and said second logic circuit in respective synchronous time domains.

2. The apparatus of claim 1, wherein said integrated circuit comprises a field programmable gate array (FPGA), and wherein each said dual-port memory comprises a block random access memory (BRAM).

3. The apparatus of claim 1, wherein each said asynchronous receiver comprises:

a deserializer in communication with said interconnection network; and

control logic in communication with a respective one of said FIFO control logic.

4. The apparatus of claim 1, wherein each said asynchronous driver comprises:

a serializer in communication with said interconnection network; and

control logic in communication with a respective one of said FIFO control logic.

5. The apparatus of claim 1, wherein said first FIFO logic and said second FIFO logic are configured for asynchronous communication of a FIFO control signal between one another.

7. The apparatus of claim 1, wherein said interconnection network comprises a mesh network.

8. The apparatus of claim 1, wherein said interconnection network comprises a crossbar switch.

6. The apparatus 5, wherein said integrated circuit comprises a field programmable gate array (FPGA), and wherein said asynchronous communication of said FIFO control signal is over programmable interconnect of said FPGA.

9. A method for communication in an integrated circuit having a first logic circuit, a second logic circuit, first first-in-first-out (FIFO) logic, second FIFO logic, and an interconnection network, the method comprising;

communicating data between said first logic circuit and said first FIFO logic in a first synchronous time domain, said communicating data between said first logic circuit and said first FIFO logic comprising;

pushing said data into a first FIFO memory; and

popping said data from said first FIFO memory to an asynchronous driver in communication with said interconnection network;

serially communicating said data between said first FIFO logic and said second FIFO logic over said interconnection network in an asynchronous time domain; and

communicating said data between said second FIFO logic and said second logic circuit in a second synchronous time domain, said communicating said data between said second FIFO logic and said second logic circuit comprising;

pushing said data into a second FIFO memory from an asynchronous receiver in communication with said interconnection network; and

popping said data from said second FIFO memory.

10. The method of claim 9, wherein said step of communicating data between said first FIFO logic and said second FIFO logic comprises:

transmitting said data from said asynchronous driver to said asynchronous receiver.

11. The method of claim 9, wherein said step of popping said data from said first FIFO memory comprises:

reading an empty flag state of said first FIFO memory at said asynchronous driver.

12. The method of claim 9, further comprising:

reading an almost-full flag state of said second FIFO memory; and

sending data indicative of said almost-full flag state to said first FIFO logic asynchronously.

13. The method of claim 9, wherein said integrated circuit comprises a field programmable gate array (FPGA), and wherein each of said first FIFO memory and said second FIFO memory comprise a block random access memory (BRAM).

14. An integrated circuit, comprising:

a first logic circuit;

a second logic circuit;

an interconnection network comprising a mesh network formed inside a programmable logic device (PLD) and separate from the programmable interconnect structure of said PLD;

first first-in-first-out (FIFO) logic coupled to said first logic circuit and said interconnection network;

second FIFO logic coupled to said second logic circuit and said interconnection network;

each said first FIFO logic and said second FIFO logic configured for asynchronous serial communication over said interconnection network; and

each said first FIFO logic and said second FIFO logic configured to respectively communicate with each said first logic circuit and said second logic circuit in respective synchronous time domains.

15. The integrated circuit of claim 14, wherein each said first FIFO logic and said second FIFO logic comprises:

a dual-port memory having a write port and a read port;

FIFO control logic configured to implement a FIFO using said dual-port memory;

an asynchronous receiver in communication with said write port; and

an asynchronous driver in communication with said read port.

16. The integrated circuit of claim 14, wherein said interconnection network comprises a crossbar switch.