Semiconductor memory device and semiconductor device and semiconductor memory device control method
First Claim
1. A semiconductor memory device comprising:
- a memory cell array having a plurality of memory cells arranged in an array form;
a word line driving circuit receiving a constant voltage that does not depend on a provided power supply voltage as a driving voltage and driving a selected word line by the constant voltage;
a sense amplifier amplifying a high level voltage of a selected bit line to the power supply voltage; and
a peripheral circuit of said memory cell array including a circuit for generating a signal defining a transition timing of a control signal to said memory cell array and/or a pulse width of the control signal;
said circuit for generating the signal including a delay circuit for delaying an input signal;
said delay circuit having a characteristic in which a delay time thereof decreases more when the provided power supply voltage is low than when the provided power supply voltage is high.
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Accused Products
Abstract
A cell core unit and its peripheral circuit are driven by a relatively low voltage power supply. A constant voltage that does not depend on the power supply voltage is provided as a boosted voltage (VBOOST) to be supplied to a control signal for a word line of the cell core unit. A sense amplifier amplifies a higher voltage level of a bit line to the power supply voltage. Then, a circuit for generating a signal for defining the transition timing and/or the pulse width of a control signal from the peripheral circuit to the cell core unit performs signal delay using a delay circuit having a characteristic in which a delay time thereof decreases with reduction of the provided power supply voltage.
75 Citations
47 Claims
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1. A semiconductor memory device comprising:
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a memory cell array having a plurality of memory cells arranged in an array form; a word line driving circuit receiving a constant voltage that does not depend on a provided power supply voltage as a driving voltage and driving a selected word line by the constant voltage; a sense amplifier amplifying a high level voltage of a selected bit line to the power supply voltage; and a peripheral circuit of said memory cell array including a circuit for generating a signal defining a transition timing of a control signal to said memory cell array and/or a pulse width of the control signal; said circuit for generating the signal including a delay circuit for delaying an input signal; said delay circuit having a characteristic in which a delay time thereof decreases more when the provided power supply voltage is low than when the provided power supply voltage is high. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35)
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36. A semiconductor memory device comprising:
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a memory cell array having a plurality of memory cells arranged in an array form; a word line driving circuit receiving a constant voltage that does not depend on a provided power supply voltage as a driving voltage and driving a selected word line by the constant voltage; a sense amplifier amplifying a high level voltage of a selected bit line to the power supply voltage; a plurality of power systems including a relatively high voltage power supply and a relatively low voltage power supply; a peripheral circuit in said memory cell array being driven by the relatively low voltage power supply; a circuit for generating a signal for defining a transition timing of a control signal supplied from said peripheral circuit to said memory cell array and/or a pulse width of the control signal including a delay circuit having a characteristic in which a delay time thereof becomes shorter when the provided power supply voltage is low than when the provided power supply voltage is high, the delay circuit being driven by the relatively low voltage power supply; a reference voltage circuit for generating a reference voltage that does not depend on the power supply voltage and is used for a boosted voltage to be supplied to said memory cell array; and a booster circuit for supplying a constant boosted voltage that does not depend on the power supply voltage based on the reference voltage, wherein said memory cell array is driven by the relatively low voltage power supply. - View Dependent Claims (37)
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38. A method of controlling a semiconductor memory device comprising a memory cell array having a plurality of memory cells arranged in an array form, a word line driving circuit for selecting a word line of said memory cell array, and a sense amplifier connected to bit lines, said method comprising the steps of:
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generating a constant voltage that does not depend on a provided power supply voltage; receiving by said word line driving circuit the generated constant voltage as a driving voltage for driving a selected word line by the constant voltage; amplifying by said sense amplifier a higher voltage level of a selected bit line to the power supply voltage; and delaying an input signal by a delay circuit when a peripheral circuit for said memory cell array generates a signal for defining a transition timing and/or a pulse width of the control signal to said memory cell array; wherein said delay circuit has a characteristic in which a delay time thereof decreases more when the provided power supply voltage is lower than when the provided power supply voltage is higher. - View Dependent Claims (39, 40, 41, 42)
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43. A method of controlling a semiconductor memory device comprising a memory cell array having a plurality of memory cells arranged in an array form, a word line driving circuit for selecting a word line of said memory cell array, and a sense amplifier connected to bit lines, said method comprising the steps of:
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generating a constant voltage that does not depend on a provided power supply voltage; receiving by said word line driving circuit the generated constant voltage as a driving voltage for driving a selected word line by the constant voltage; amplifying by said sense amplifier a higher voltage level of a selected bit line to the power supply voltage; driving said memory cell array and a peripheral circuit thereof by a relatively low voltage power supply; supplying the constant voltage that does not depend on the power supply voltage as a boosted voltage to be supplied to a control signal for said memory cell array; and performing signal delay using a delay circuit having a characteristic in which a delay time thereof decreases with reduction of the provided power supply voltage, by a circuit for generating the signal for defining a transition timing and/or a pulse width of the control signal supplied from said peripheral circuit to said memory cell array.
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44. A method of controlling a semiconductor memory device comprising a memory cell array having a plurality of memory cells arranged in an array form, a word line driving circuit for selecting a word line of said memory cell array, and a sense amplifier connected to bit lines, said method comprising the steps of:
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generating a constant voltage that does not depend on a provided power supply voltage; receiving by said word line driving circuit the generated constant voltage as a driving voltage for driving a selected word line by the constant voltage; amplifying by said sense amplifier a higher voltage level of a selected bit line to the power supply voltage; performing signal delay using a delay circuit having a reverse characteristic in which a delay time thereof decreases with reduction of the provided power supply voltage, by a circuit for generating a signal for defining a transition timing and/or a pulse width of a control signal supplied from a peripheral circuit of said memory cell array to said memory cell array; driving said peripheral circuit by the power supply voltage; driving said delay circuit by a stepped-down power supply voltage obtained by stepping down the power supply voltage; supplying the constant voltage that does not depend on rise and fall of the power supply voltage as a boosted voltage to be supplied to a control signal for said memory cell array; and driving said memory cell array by the stepped-down power supply voltage obtained by stepping down the power supply voltage.
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45. A semiconductor memory device comprising:
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a memory cell array having a plurality of memory cells arranged in an array form; a word line driving circuit receiving a constant voltage that does not depend on a provided power supply voltage as a driving voltage and driving a selected word line by the constant voltage; a sense amplifier amplifying a high level voltage of a selected bit line to the power supply voltage, voltage step down circuit outputting a voltage that is lower than said power supply voltage; and a peripheral circuit which comprises a circuit that generates a signal for determining the transition timing of a control signal for said memory cell array and/or the pulse width of the control signal; said peripheral circuit comprising a delay circuit that delays a received signal; said delay circuit being driven by the output voltage from said step down circuit, wherein said memory cell array is driven by the output voltage from said voltage step-down circuit, said delay circuit having a characteristic in which a delay time thereof decreases more when the provided power supply voltage is low than when the provided power supply voltage is high. - View Dependent Claims (46, 47)
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Specification