Internally asymmetric methods and circuits for evaluating static memory cell dynamic stability

• US 7,301,835 B2
• Filed: 09/13/2005
• Issued: 11/27/2007
• Est. Priority Date: 09/13/2005
• Status: Expired due to Fees

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: International Business Machines Corporation
• Inventors: Joshi, Rajiv V., Devgan, Anirudh, Ye, Qiuyi
• Primary Examiner(s): Zarabian; Amir
• Assistant Examiner(s): Graham; Kretelia
• Application Number:
  US11/225,652
• Publication Number:
  US 20070058466A1
• Time in Patent Office: 805 Days
• Field of Search: 365/201, 365/189.03, 365/189.05
• US Class Current: 365/201
• CPC Class Codes: G11C 11/41 forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
• CPC Class Codes: G11C 2029/5002 Characteristic
• CPC Class Codes: G11C 29/006 at wafer scale level, i.e. wafer scale integration [WSI]
• CPC Class Codes: G11C 29/12005 comprising voltage or current generators
• CPC Class Codes: G11C 29/24 Accessing extra cells, e.g. dummy cells or redundant cells
• CPC Class Codes: G11C 29/50 Marginal testing, e.g. race, voltage or current testing

Abstract

Internally asymmetric methods and circuits for evaluating static memory cell dynamic stability provide a mechanism for raising the performance of memory arrays beyond present levels/yields. By altering the internal symmetry of a static random access memory (SRAM) memory cell, operating the cell and observing changes in performance caused by the asymmetric operation, the dynamic stability of the SRAM cell can be studied over designs and operating environments. The asymmetry can be introduced by splitting one or both power supply rail inputs to the cell and providing differing power supply voltages or currents to each cross-coupled stage. Alternatively or in combination, the loading at the outputs of the cell can altered in order to affect the performance of the cell. A memory array with at least one test cell can be fabricated in a production or test wafer and internal nodes of the memory cell can be probed to provide further information.

Claims

1. A memory device, comprising:

at least one test memory cell comprising a symmetric storage latch including a first inverter stage and a second inverter stage with an output of the first inverter stage providing an input to the second inverter stage and an output of the second inverter stage providing an input to the first inverter stage whereby a state of said at least one test memory cell is statically maintained;

a first plurality of other memory cells coupled to at least one bitline to form a column;

a second plurality of other memory cells coupled to at least one other bitline to form at least one other column; and

an asymmetric pair of connections, a first connection coupled to said first inverter stage and a second connection coupled to said second inverter stage, whereby a stability of said at least one test memory cell is evaluated by varying an asymmetry between said pair of connections and observing operation of said at least one memory cell, wherein said asymmetry is not applied to said first plurality of other memory cells, wherein said at least one test memory cell is coupled to said at least one bitline via a corresponding pass device, whereby a value of said at least one test memory cell is read or written by enabling said at least one pass device, and wherein each of said first plurality of other memory cells include other corresponding pass devices to isolate said first plurality of other memory cells from said at least one bitline while said at least one test memory cell is read to or written from, and wherein said memory device includes a secondary pass device coupled between said at least one other bitline and said at least one bitline, and a control logic for controlling a conduction state of said secondary pass device whereby a loading on said at least one test memory cell is adjusted by said control logic for testing reads from and writes to said at least one test memory cell over a selectable set of loads.

2. A memory device, comprising:

at least one test memory cell comprising a symmetric storage latch including a first inverter stage and a second inverter stage with an output of the first inverter stage providing an input to the second inverter stage and an output of the second inverter stage providing an input to the first inverter stage whereby a state of said at least one test memory cell is statically maintained;

an asymmetric pair of connections, a first connection coupled to said first inverter stage and a second connection coupled to said second inverter stage, whereby a stability of said memory cell is evaluated by varying an asymmetry between said pair of connections and observing operation of said at least one test memory cell, wherein said at least one test memory cell is coupled to at least one bitline of said memory device via a corresponding pass device, whereby a value of said at least one test memory cell is read or written by enabling said at least one pass device; and

a first plurality of other memory cells coupled to said at least one bitline to form a column, and wherein each of said first plurality of other memory cells includes at least one other pass device to isolate said first plurality of other memory cells from said at least one bitline while said at least one test memory cell is read to or written from;

a second plurality of other memory cells having corresponding pass devices connected to at least one other bitline;

a secondary pass device coupled between said at least one other bitline and said at least one bitline; and

a control logic for controlling a conduction state of said secondary pass device whereby a loading on said at least one test memory cell is adjusted by said control logic for testing reads from and writes to said at least one test memory cell over a selectable set of loads.