Memory access engine having multi-level command structure

• US 7,302,503 B2
• Filed: 04/01/2003
• Issued: 11/27/2007
• Est. Priority Date: 04/01/2002
• Status: Expired due to Fees

• Current Assignee: Broadcom Corporation (Broadcom, Inc.)
• Original Assignee: Broadcom Corporation (Broadcom, Inc.)
• Inventors: MacInnis, Alexander G.
• Primary Examiner(s): Gaffin; Jeffrey
• Assistant Examiner(s): Nguyen; Tanh Q.
• Application Number:
  US10/404,074
• Publication Number:
  US 20040047194A1
• Time in Patent Office: 1,701 Days
• Field of Search: 710/22, 710/23, 710/24, 710/28, 710/52, 710/54, 710/53, 710 55- 57
• US Class Current: 710/22
• CPC Class Codes: G06F 13/28 using burst mode transfer, e.g. direct memory access DMA, cycle steal G06F13/32 takes precedence
• CPC Class Codes: G06T 1/60 Memory management

Abstract

A direct memory access system utilizing a local memory that stores a plurality of DMA command lists, each comprising at least one DMA command. A command queue can hold a plurality of entries, each entry comprising a pointer field and a sequence field. The pointer field points to one of the DMA command lists. The sequence field holds a sequence value. A DMA engine accesses an entry in the command queue and then accesses the DMA commands of the DMA command list pointed to by the pointer field of the accessed entry. The DMA engine performs the DMA operations specified by the accessed DMA commands. The DMA engine makes available the sequence value held in the sequence field of the accessed entry when all of the DMA commands in the accessed command list have been performed. In one embodiment, the command queue is part of the DMA engine.

Claims

1. A direct memory access (DMA) system comprising:

a memory element storing a plurality of DMA command lists, at least one of said lists comprising more than one DMA command;

a command queue adapted to hold a plurality of entries, each entry comprising a pointer field and a sequence field, the pointer field pointing to one of the DMA command lists, the sequence field holding a sequence value indicative of a sequential placement of said entry in the command queue; and

a DMA engine adapted to access an entry in the command queue and to access the DMA commands of the DMA command list pointed to by the pointer field of the accessed entry, the DMA engine further adapted to perform DMA operations specified by the accessed DMA commands, the DMA engine further adapted to make available the sequence value held in the sequence field of the accessed entry when all of the DMA commands in the accessed command list have been performed.

2. The DMA system of claim 1 wherein the command queue is included in the DMA engine.

3. The DMA system of claim 1 wherein a last DMA command in each command list includes an indication that it is the last command in the list.

4. The DMA system of claim 1 further comprising a processor adapted to provide the entries to the command queue in order to effect the performance of corresponding DMA operations.

5. The DMA system of claim 4 wherein the DMA engine is adapted to provide the sequence value to the processor when all of the DMA commands in the accessed command list have been performed.

6. The DMA system of claim 1 wherein when all of the DMA commands in the accessed command list have been performed, the DMA engine is adapted to access a next entry in the command queue and to access the DMA commands of the DMA command list pointed to by the pointer field of the accessed entry, the DMA engine further adapted to perform DMA operations specified by the accessed DMA commands, the DMA engine further adapted to make available the sequence value held in the sequence field of the accessed entry when all of the DMA commands in the accessed command list have been performed.

7. The DMA system of claim 1 wherein the memory element is a static RAM memory element.

8. A method of implementing direct memory access (DMA) comprising:

storing a plurality of DMA command lists, at least one of said lists comprising more than one DMA command;

maintaining a command queue adapted to hold a plurality of entries, each entry comprising a pointer field and a sequence field, the pointer field pointing to one of the DMA command lists, the sequence field holding a sequence value indicative of a sequential placement of said entry in the command queue;

accessing an entry in the command queue;

accessing the DMA commands of the DMA command list pointed to by the pointer field of the accessed entry;

performing DMA operations specified by the accessed DMA commands; and

making available the sequence value held in the sequence field of the accessed entry when all of the DMA commands in the accessed command list have been performed.

9. The method of claim 8 wherein a last DMA command in each command list includes an indication that it is the last command in the list.

10. The method of claim 8 wherein a processor provides the entries to the command queue in order to effect the performance of corresponding DMA operations.

11. The method of claim 10 wherein making available the sequence value comprises providing the sequence value to the processor when all of the DMA commands in the accessed command list have been performed.

12. The method of claim 8 wherein the plurality of DMA command lists are stored in a static RAM memory element.

13. The method of claim 8 further comprising:

when all of the DMA commands in the accessed command list have been performed, accessing a next entry in the command queue;

accessing the DMA commands of the DMA command list pointed to by the pointer field of the accessed entry;

performing DMA operations specified by the accessed DMA commands; and

making available the sequence value held in the sequence field of the accessed entry when all of the DMA commands in the accessed command list have been performed.

14. A digital media processing system comprising:

a memory element storing a plurality of direct memory access (DMA) command lists, at least one of said lists comprising more than one DMA command;

a command queue adapted to hold a plurality of entries, each entry comprising a pointer field and a sequence field, the pointer field pointing to one of the DMA command lists, the sequence field holding a sequence value indicative of a sequential placement of said entry in the command queue;

a media processor adapted to process digital media data elements and adapted to provide entries to the command queue in order to effect the performance of corresponding DMA operations, each entry corresponding to a specified media data element; and

a DMA engine adapted to access an entry in the command queue and to access the DMA commands of the DMA command list pointed to by the pointer field of the accessed entry, the DMA engine further adapted to perform DMA operations specified by the accessed DMA commands, the DMA engine further adapted to provide the sequence value held in the sequence field of the accessed entry to the media processor when all of the DMA commands in the accessed command list have been performed.

15. The digital media processing system of claim 14 wherein the command queue is included in the DMA engine.

16. The digital media processing system of claim 14 wherein a last DMA command in each command list includes an indication that it is the last command in the list.

17. The digital media processing system of claim 14 wherein when all of the DMA commands in the accessed command list have been performed, the DMA engine is adapted to access a next entry in the command queue and to access the DMA commands of the DMA command list pointed to by the pointer field of the accessed entry, the DMA engine further adapted to perform DMA operations specified by the accessed DMA commands, the DMA engine further adapted to provide the sequence value held in the sequence field of the accessed entry to the media processor when all of the DMA commands in the accessed command list have been performed.

18. The digital media processing system of claim 14 wherein the memory element is a static RAM memory element.

19. The digital media processing system of claim 14 wherein the media processor is a video processor adapted to process digital video data elements and adapted to provide entries to the command queue in order to effect the performance of corresponding DMA operations, each entry corresponding to a specified video data element.

20. The digital media processing system of claim 19 wherein the video processor is adapted to process macroblock data elements and adapted to provide entries to the command queue in order to effect the performance of corresponding DMA operations, each entry corresponding to a specified macroblock data element.