System and method for unfolding/replicating logic paths to facilitate propagation delay modeling

• US 7,302,659 B2
• Filed: 02/10/2005
• Issued: 11/27/2007
• Est. Priority Date: 02/10/2005
• Status: Expired due to Fees

• Current Assignee: Google LLC (Alphabet Inc.)
• Original Assignee: International Business Machines Corporation
• Inventors: Nelson, Bradley S., Ja, Yee
• Primary Examiner(s): Kik; Phallaka
• Application Number:
  US11/054,903
• Publication Number:
  US 20060190883A1
• Time in Patent Office: 1,020 Days
• Field of Search: 716/7, 716/6, 703/16
• US Class Current: 716/106
• CPC Class Codes: G06F 30/3312 Timing analysis

Abstract

A system and method for unfolding/replicating logic paths to facilitate propagation delay modeling are provided. With the system and method, nets of an integrated circuit design are unfolded and logic of these nets is replicated such that each leg of a fanout can be driven independently from the signal source. In order to unfold the nets, the nets and logic are replicated in the netlist and connected to replicated source and endpoints. These new nets in the netlist may then be driven separately such that a different propagation delay along different nets from the same source may be simulated. In this way, a level of propagation delay may be abstracted into the modeling by driving or delaying each path separately. The transitioning value will then appear to have differing arrival times from the perspective of the sinks.

Claims

1. A method, in a data processing system, for modeling an operation of an integrated circuit design, comprising:

receiving data representing the integrated circuit design;

identifying an original path in the integrated circuit design requiring unfolding, wherein the original path starts at a source and ends at two or more sinks;

unfolding the original path such that one or more new nets are provided, wherein each of the one or more new nets is driven from a differently delayed source from that of the original path; and

modeling an operation of the integrated circuit design using the original net and the one or more new nets in the path such that each of the original path and the one or more new nets provides a different propagation delay at the two or more sinks and a transitioning value has differing arrival times at the two or more sinks.

2. The method of claim 1, further comprising:

determining if a logic gate in the original path requires replication; and

replicating the logic gate if the logic gate needs to be replicated.

3. The method of claim 1, wherein the one or more new nets are added to a netlist for the integrated circuit design and wherein the one or more new nets are connected to one or more of a replicated source and a replicated endpoint of the original net.

4. The method of claim 1, wherein unfolding the original path includes:

generating a new endpoint net for a replicated path if the new endpoint net has not already been generated for a previous path;

generating a new start point net; and

replicating zero or more gates in the original path for the replicated path.

5. The method of claim 4, wherein replicating zero or more gates in the original path for the replicated path includes:

determining, for each output of each replicated gate, if a sink of an output of the replicated gate is the new endpoint net; and

connecting the replicated gate to the endpoint net if the sink of the output of the replicated gate is the new endpoint net.

6. The method of claim 4, wherein replicating zero or more gates in the original path for the replicated path includes:

determining if a replicated sink gate for the original path exists;

determining if a replicated output net for the original path exists; and

connecting output of the zero or more replicated gates to the replicated output net, if the replicated sink gate for the original path exists and the replicated output net for the original path exists.

7. The method of claim 6, wherein if a replicated sink gate for the original path does exist, and a replicated output net for the original path does not exist, an output net of the original gate in the original path is replicated and the replicated gate is connected to the replicated output net of the original gate.

8. The method of claim 4, wherein replicating zero or more gates in the original path for the replicated path includes:

determining, for each input of the original gate, if a source of an input of the original gate is the new start point net; and

connecting the replicated gate to the new start point net if the source of the input to the original gate is the new start point net.

9. The method of claim 4, wherein replicating zero or more gates in the original path for the replicated path includes:

determining if a replicated input net for the original path exists; and

connecting an input of the replicated gate to the replicated input net if the replicated input net exists.

10. The method of claim 1, wherein identifying an original path in the integrated circuit design requiring unfolding includes at least one of identifying paths in the integrated circuit design in which a common source drives more than one path and identifying asynchronous interface paths.

11. A computer program product comprising a computer readable medium comprising instructions, wherein the instructions, when executed by a computing device, cause the computing device to execute a method for modeling an operation of an integrated circuit design, the instructions comprising:

first instructions for receiving data representing the integrated circuit design;

second instructions for identifying an original path in the integrated circuit design requiring unfolding, wherein the original path starts at a source and ends at two or more sinks;

third instructions for unfolding the original path such that one or more new nets are provided, wherein each of the one or more new nets is driven from a differently delayed source from that of the original path; and

fourth instructions for modeling an operation of the integrated circuit design using the original net and the one or more new nets such that each of the original path and the one or more new nets provides a different propagation delay at the two or more sinks and a transitioning value has differing arrival times at the two or more sinks.

12. The computer program product of claim 11, further comprising:

fifth instructions for determining if a logic gate in the original path requires replication; and

sixth instructions for replicating the logic gate if the logic gate needs to be replicated.

13. The computer program product of claim 11, wherein the one or more new nets are added to a netlist for the integrated circuit design and wherein the one or more new nets are connected to one or more of a replicated source and a replicated endpoint of the original net.

14. The computer program product of claim 11, wherein the third instructions for unfolding an original net in the original path include:

instructions for generating a new endpoint net for a replicated path if the new endpoint net has not already been generated for a previous path;

instructions for generating a new start point net; and

instructions for replicating zero or more gates in the original path for the replicated path.

15. The computer program product of claim 14, wherein the instructions for replicating zero or more gates in the original path for the replicated path include:

instructions for determining, for each output of each replicated gate, if a sink of an output of the replicated gate is the new endpoint net; and

instructions for connecting the replicated gate to the new endpoint net if the sink of the output of the replicated gate is the new endpoint net.

16. The computer program product of claim 14, wherein the instructions for replicating zero or more gates in the original path for the replicated path include:

instructions for determining if a replicated sink gate for the original path exists;

instructions for determining if a replicated output net for the original path exists; and

instructions for connecting output of the zero or more replicated gates to the replicated output net, if the replicated sink gate for the original path exists and the replicated output net for the original path exists.

17. The computer program product of claim 16, wherein if a replicated sink gate for the original path does exist, and a replicated output net for the original path does not exist an output net of the original gate in the original path is replicated and the replicated gate is connected to the replicated output net of the original gate.

18. The computer program product of claim 14, wherein the instructions for replicating zero or more gates in the original path for the replicated path include:

instructions for determining, for each input of the original gate, if a source of an input of the original gate is the new start point net; and

instructions for connecting the replicated gate to the new start point net if the source of the input to the original gate is the new start point net.

19. The computer program product of claim 14, wherein the instructions for replicating zero or more gates in the original path for the replicated path includes:

instructions for determining if a replicated input net for the original path exists; and

instructions for connecting an input of the replicated gate to the replicated input net if the replicated input net exists.

20. A system for modeling an operation of an integrated circuit design, comprising:

means for receiving data representing the integrated circuit design;

means for identifying an original path in the integrated circuit design requiring unfolding, wherein the original Dath starts at a source and ends at two or more sinks;

means for unfolding the original path such that one or more new nets are provided, wherein each of the one or more new nets is driven from a differently delayed source from that of the original path; and

means for modeling an operation of the integrated circuit design using the original net and the one or more new nets such that each of the original path and the one or more new nets provides a different propagation delay at the two or more sinks and a transitioning value has differing arrival times at the two or more sinks.