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System and method for unfolding/replicating logic paths to facilitate propagation delay modeling

  • US 7,302,659 B2
  • Filed: 02/10/2005
  • Issued: 11/27/2007
  • Est. Priority Date: 02/10/2005
  • Status: Expired due to Fees
First Claim
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1. A method, in a data processing system, for modeling an operation of an integrated circuit design, comprising:

  • receiving data representing the integrated circuit design;

    identifying an original path in the integrated circuit design requiring unfolding, wherein the original path starts at a source and ends at two or more sinks;

    unfolding the original path such that one or more new nets are provided, wherein each of the one or more new nets is driven from a differently delayed source from that of the original path; and

    modeling an operation of the integrated circuit design using the original net and the one or more new nets in the path such that each of the original path and the one or more new nets provides a different propagation delay at the two or more sinks and a transitioning value has differing arrival times at the two or more sinks.

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