High performance stress-enhanced MOSFETs using Si:C and SiGe epitaxial source/drain and method of manufacture

• US 7,303,949 B2
• Filed: 10/20/2003
• Issued: 12/04/2007
• Est. Priority Date: 10/20/2003
• Status: Active Grant

• Current Assignee: Auriga Innovations, Inc. (Quarterhill Inc. (f/k/a Wi-LAN Inc.))
• Original Assignee: International Business Machines Corporation
• Inventors: Chen, Huajie, Chidambarrao, Dureseti, Dokumaci, Omer H
• Primary Examiner(s): Whitehead, Jr.; Carl
• Assistant Examiner(s): Mitchell; James M
• Application Number:
  US10/689,506
• Publication Number:
  US 20050082616A1
• Time in Patent Office: 1,506 Days
• Field of Search: 438/199, 257/369
• US Class Current: 438/199
• CPC Class Codes: H01L 21/3081 characterised by their composition, e.g. multilayer masks, materials
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823814 with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
• CPC Class Codes: H01L 27/092 complementary MIS field-effect transistors
• CPC Class Codes: H01L 29/1054 with a variation of the composition, e.g. channel with strained layer for increasing the mobility
• CPC Class Codes: H01L 29/66628 recessing the gate by forming single crystalline semiconductor material at the source or drain location
• CPC Class Codes: H01L 29/66636 with source or drain recessed by etching or first recessed by etching and then refilled
• CPC Class Codes: H01L 29/7848 the means being located in the source/drain region, e.g. SiGe source and drain
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A semiconductor device and method of manufacturing a semiconductor device. The semiconductor device includes channels for a pFET and an nFET. A SiGe layer is selectively grown in the source and drain regions of the pFET channel and a Si:C layer is selectively grown in source and drain regions of the nFET channel. The SiGe and Si:C layer match a lattice network of the underlying Si layer to create a stress component. In one implementation, this causes a compressive component in the pFET channel and a tensile component in the nFET channel.

Claims

1. A method of manufacturing a semiconductor structure, comprising the steps of:

forming a p-type field-effect-transistor (pFET) channel and a n-type field-effect-transistor (nFET) channel in a substrate;

forming a pFET stack in the pFET channel and an nFET stack in the nFET channel;

providing a first layer of material at source/drain regions associated with the pFET stack, the first layer of material having a lattice constant different than a base lattice constant of the substrate to create a compressive state within the pFET channel; and

providing a second layer of material at the source/drain regions associated with the nFET stack, the second layer of material having a lattice constant different than the base lattice constant of the substrate to create a tensile state at the nFET channel;

the first layer of material being formed by placing a mask over the nFET channel and etching the regions of the pFET and selectively growing the first layer of material within the regions of the pFET channel, and the second layer of material being formed by placing a mask over the pFET channel and etching regions of the nFET and selectively growing the second layer of material within the regions of the nFET channel;

providing a protection layer under the mask and over the nFET stack prior to the etching of the regions of the pFET stack and selectively growing the first layer of material; and

providing a protection layer under the mask and over the nFET stack prior to the etching of the regions of the pFET stack and selectively growing the second layer of material.

2. A method of manufacturing a semiconductor structure, comprising the steps of:

forming a p-type field-effect-transistor (pFET) channel and a n-type field-effect-transistor (nFET) channel in a substrate;

forming a pFET stack in the pFET channel and an nFET stack in the nFET channel;

after the pFET stack is formed, providing a first layer of material at source/drain regions associated with the pFET stack, the first layer of material having a lattice constant different than a base lattice constant of the substrate to create a compressive state within the pFET channel; and

after the nFET stack is formed, providing a second layer of material at the source/drain regions associated with the nFET stack, the second layer of material having a lattice constant different than the base lattice constant of the substrate to create a tensile state at the nFET channel,

wherein the first layer of material is formed by placing a mask over the nFET stack, etching the regions of the pFET, and selectively growing the first layer of material within the regions of the pFET channel;

wherein the second layer of material is formed by placing a mask over the pFET stack, etching regions of the nFET, and selectively growing the second layer of material within the regions of the nFET channel; and

wherein the first layer of material and the second layer of material are each grown to a thickness about 10 to 100 nm.

3. A method of manufacturing a semiconductor structure, comprising the steps of:

forming a p-type field-effect-transistor (pFET) channel and a n-type field-effect-transistor (nFET) channel in a substrate;

forming a pFET stack in the pFET channel and an nFET stack in the nFET channel;

after the pFET stack is formed, providing a first layer of material at source/drain regions associated with the pFET stack, the first layer of material having a lattice constant different than a base lattice constant of the substrate to create a compressive state within the pFET channel; and

after the nFET stack is formed, providing a second layer of material at the source/drain regions associated with the nFET stack, the second layer of material having a lattice constant different than the base lattice constant of the substrate to create a tensile state at the nFET channel,

wherein the first aver of material is formed by placing a mask layer the nFET stack, etching the regions of the pFET, and selectively growing the first layer of material within the regions of the pFET channel;

wherein the second layer of material is formed by placing a mask over the pFET stack, etching regions of the nFET, and selectively growing the second layer of material within the regions of the nFET channel; and

wherein the first layer of material and the second layer of material are embedded in the layer.