Contact structure of a wires and method manufacturing the same, and thin film transistor substrate including the contact structure and method manufacturing the same

• US 7,303,987 B2
• Filed: 04/02/2002
• Issued: 12/04/2007
• Est. Priority Date: 04/26/2001
• Status: Expired due to Term

• Current Assignee: Samsung Display Company Limited (Samsung Electronics Co. Ltd.)
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Hong, Mun-Pyo, Song, Young-Joo, Song, Keun-Kyu, Roh, Nam-Seok, Lim, Seung-Taek, Choi, Kwon-Young, Kwak, Sang-Ki
• Primary Examiner(s): Menz; Douglas M.
• Application Number:
  US10/475,903
• Publication Number:
  US 20040238825A1
• Time in Patent Office: 2,072 Days
• Field of Search: 257/79, 257/758, 257/774, 438/625, 438/637
• US Class Current: 438/625
• CPC Class Codes: G02F 1/13458 Terminal pads
• CPC Class Codes: G02F 1/136227 Through-hole connection of the pixel electrode to the active element through an insulation layer
• CPC Class Codes: G02F 1/136286 Wiring, e.g. gate line, drain line
• CPC Class Codes: G02F 1/13629 Multilayer wirings
• CPC Class Codes: H01L 21/76805 the opening being a via or contact hole penetrating the underlying conductor
• CPC Class Codes: H01L 21/76816 Aspects relating to the layout of the pattern or to the size of vias or trenches layout of the interconnections per se H01L23/528; CAD of ICs G06F30/00
• CPC Class Codes: H01L 23/53223 Additional layers associated with aluminium layers, e.g. adhesion, barrier, cladding layers
• CPC Class Codes: H01L 27/124 with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits wiring structures per se H01L23/52
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

In a method of fabricating a thin film transistor array substrate for a liquid crystal display, a gate line assembly is formed on a substrate with a chrome-based under-layer and an aluminum alloy-based over-layer while proceeding in the horizontal direction. The gate line assembly has gate lines, and gate electrodes, and gate pads. A gate insulating layer is deposited onto the insulating substrate such that the gate insulating layer covers the gate line assembly. A semiconductor layer and an ohmic contact layer are sequentially formed on the gate insulating layer. A data line assembly is formed on the ohmic contact layer with a chrome-based under-layer and an aluminum alloy-based over-layer. The data line assembly has data lines crossing over the gate lines, source electrodes, drain electrodes, and data pads. A protective layer is deposited onto the substrate, and patterned to thereby form contact holes exposing the drain electrodes, the gate pads, and the data pads. The sidewall of the under-layers for the gate line assembly and the data line assembly is exposed through the contact holes. An IZO-based layer is deposited onto the substrate, and patterned to thereby form pixel electrodes, subsidiary gate pads, and subsidiary data pads. The pixel electrodes are connected to the sidewall of the drain electrodes, and the subsidiary gate and data pads are connected to the sidewall of the gate and the data pads.

Claims

1. A method of forming a wiring line contact structure, the method comprising:

forming a wiring line assembly having a first a conductive layer on a surface of a substrate, wherein the first conductive layer has at least two layers having the same planar shape and a sidewall that is inclined relative to the surface;

depositing an insulating layer onto the wiring line assembly such that the insulating layer covers the wiring line assembly;

patterning the insulating layer to thereby form a contact hole exposing the sidewall of the wiring line assembly; and

,

forming a second conductive layer such that the second conductive layer contacts the sidewall of the wiring line assembly through the contact hole.

2. The method of claim 1, wherein the first conductive layer is formed with an over-layer based on aluminum or aluminum alloy, and an under-layer based on molybdenum, molybdenum alloy or chrome.

3. The method of claim 1, wherein the distance between the boundary of the contact hole and the boundary of the wiring line assembly is established to be 2 μ

m or less.

4. The method of claim 1, wherein the second conductive layer is formed with a transparent conductive material.

5. The method of claim 4, wherein the transparent conductive material is indium zinc oxide (IZO).

6. A wiring line contact structure, comprising:

a wiring line assembly formed on a surface of a substrate, wherein the wiring line assembly has at least two conductive layers having the same planar share and a sidewall that is inclined relative to the surface;

an insulating layer covering the wiring line assembly, the insulating layer having a contact hole exposing the sidewall of the wiring line assembly; and

,

a conductive layer formed on the insulating layer with IZO while contacting the sidewall of the wiring line assembly through the contact hole.

7. The wiring line contact structure of claim 6, wherein the wiring line assembly is formed with an under-layer based on chrome, molybdenum or molybdenum alloy, and an over-layer based on aluminum or aluminum alloy.