Method for fabricating a power semiconductor device having a voltage sustaining layer with a terraced trench facilitating formation of floating islands
First Claim
1. A power semiconductor device made in accordance with a method comprising the steps of:
- A. providing a substrate of a first conductivity type;
B. forming a voltage sustaining region on said substrate;
1. depositing an epitaxial layer on the substrate, said epitaxial layer having a first conductivity type;
2. forming at least one terraced trench in said epitaxial layer, said terraced trench having a plurality of portions that differ in width to define at least one annular ledge therebetween;
3. depositing a barrier material along the walls and bottom of said trench;
4. implanting a dopant of a second conductivity type through the barrier material lining said at least one annular ledge and said trench bottom and into adjacent portions of the epitaxial layer;
5. diffusing said dopant to form at least one annular doped region in said epitaxial layer and at least one other region located below said annular doped region in said epitaxial layer;
6. depositing a filler material in said terraced trench to substantially fill said terraced trench; and
C. forming over said voltage sustaining region at least one region of said second conductivity type to define a junction therebetween.
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Abstract
A method is provided for forming a power semiconductor device. The method begins by providing a substrate of a first conductivity type and then forming a voltage sustaining region on the substrate. The voltage sustaining region is formed by depositing an epitaxial layer of a first conductivity type on the substrate and forming at least one terraced trench in the epitaxial layer. The terraced trench has a plurality of portions that differ in width to define at least one annular ledge therebetween. A barrier material is deposited along the walls of the trench. A dopant of a second conductivity type is implanted through the barrier material lining the annular ledge and said trench bottom and into adjacent portions of the epitaxial layer. The dopant is diffused to form at least one annular doped region in the epitaxial layer and at least one other region located below the annular doped region. A filler material is deposited in the terraced trench to substantially fill the trench, thus completing the voltage sustaining region. At least one region of the second conductivity type is formed over the voltage sustaining region to define a junction therebetween.
25 Citations
18 Claims
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1. A power semiconductor device made in accordance with a method comprising the steps of:
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A. providing a substrate of a first conductivity type; B. forming a voltage sustaining region on said substrate; 1. depositing an epitaxial layer on the substrate, said epitaxial layer having a first conductivity type; 2. forming at least one terraced trench in said epitaxial layer, said terraced trench having a plurality of portions that differ in width to define at least one annular ledge therebetween; 3. depositing a barrier material along the walls and bottom of said trench; 4. implanting a dopant of a second conductivity type through the barrier material lining said at least one annular ledge and said trench bottom and into adjacent portions of the epitaxial layer; 5. diffusing said dopant to form at least one annular doped region in said epitaxial layer and at least one other region located below said annular doped region in said epitaxial layer; 6. depositing a filler material in said terraced trench to substantially fill said terraced trench; and C. forming over said voltage sustaining region at least one region of said second conductivity type to define a junction therebetween.
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2. A power semiconductor device made in accordance with a method comprising the steps of:
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A. providing a substrate of a first conductivity type; B. forming a voltage sustaining region on said substrate by; 1. depositing an epitaxial layer on the substrate, said epitaxial layer having a first conductivity type; 3. forming at least one terraced trench in said epitaxial layer, said terraced trench having a plurality of portions that differ in width to define at least one annular ledge therebetween; 3. depositing a barrier material along the walls and bottom of said trench; 4. implanting a dopant of a second conductivity type through the barrier material lining said at least one annular ledge and said trench bottom and into adjacent portions of the epitaxial layer; 5. diffusing said dopant to form at least one annular doped region in said epitaxial layer and at least one other region located below said annular doped region in said epitaxial layer; 7. depositing a filler material in said terraced trench to substantially fill said terraced trench; and C. forming over said voltage sustaining region at least one region of said second conductivity type to define a junction therebetween, wherein said plurality of portions of the terraced trench are coaxially located with respect to one another, and wherein said plurality of portions of the terraced trench includes at least three portions that differ in width from one another to define at least two annular ledges and said at least one annular doped region includes at least two annular doped regions, and wherein the step of forming at least one terraced trench includes the steps of successively etching said at least three portions of the terraced trench beginning with a largest width portion and ending with a smallest width portion.
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3. A power semiconductor device made in accordance with a method comprising the steps of:
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A. providing a substrate of a first conductivity type; B. forming a voltage sustaining region on said substrate by; 1. depositing an epitaxial layer on the substrate, said epitaxial layer having a first conductivity type; 4. forming at least one terraced trench in said epitaxial layer, said terraced trench having a plurality of portions that differ in width to define at least one annular ledge therebetween; 3. depositing a barrier material along the walls and bottom of said trench; 4. implanting a dopant of a second conductivity type through the barrier material lining said at least one annular ledge and said trench bottom and into adjacent portions of the epitaxial layer; 5. diffusing said dopant to form at least one annular doped region in said epitaxial layer and at least one other region located below said annular doped region in said epitaxial layer; 8. depositing a filler material in said terraced trench to substantially fill said terraced trench; and C. forming over said voltage sustaining region at least one region of said second conductivity type to define a junction therebetween, wherein step (C) further includes the steps of; forming a gate conductor above a gate dielectric region; forming first and second body regions in the epitaxial layer to define a drift region therebetween, said body regions having a second conductivity type; forming first and second source regions of the first conductivity type in the first and second body regions, respectively.
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4. A power semiconductor device comprising:
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a substrate of a first conductivity type; a voltage sustaining region disposed on said substrate, said voltage sustaining region including; an epitaxial layer having a first conductivity type; at least one terraced trench located in said epitaxial layer, said terraced trench having a plurality of regions that differ in width to define at least one annular ledge therebetween; at least one annular doped region having a dopant of a second conductivity type, said annular doped legion being located in said epitaxial layer below and adjacent to said annular ledge; a filler material substantially filling said terraced trench; and at least one active region of said second conductivity disposed over said voltage sustaining region to define a junction therebetween. - View Dependent Claims (5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18)
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Specification