Method and system for providing a digital signal representing an analog signal

• US 7,304,591 B2
• Filed: 08/11/2004
• Issued: 12/04/2007
• Est. Priority Date: 08/13/2003
• Status: Expired due to Fees

• Current Assignee: Silantrix Ltd.
• Original Assignee: Sandlinks Systems Ltd.
• Inventors: Raphaeli, Dan
• Primary Examiner(s): JEAN PIERRE, PEGUY
• Application Number:
  US10/568,079
• Publication Number:
  US 20060222128A1
• Time in Patent Office: 1,210 Days
• Field of Search: 341/143, 341/144, 341/155, 341/118, 341/120, 341/161
• US Class Current: 341/118
• CPC Class Codes: H03M 1/1205 Multiplexed conversion systems
• CPC Class Codes: H03M 1/44 Sequential comparisons in series-connected stages with change in value of analogue signal
• CPC Class Codes: H04L 7/00 Arrangements for synchronising receiver with transmitter synchronisation of generators of electric oscillations or pulses H03L7/00

Abstract

A method for providing a digital output signal (59) representing an analog input signal (54) in a system (50) including an analog circuit (51) and a control unit (52). Analog circuit (51) preferably features high bandwidth, high gain, and low current consumption. Analog circuit (51) is preferably implemented with low accuracy components. Control unit (52) keeps error outputs (55) of analog circuit (51) at a minimal value so that control unit (52) cancels analog input signal(54) by outputting discrete value signals (58) in a feedback loop as input (58) to analog circuit (51). A DSP (53) of system (50) is previously trained using known analog signals and a model relating inputs (54,58) to error outputs (55) of analog circuit (51) is previously known. During operation, a digital representation (57) of the discrete value signals (58) is fed to DSP (53) that reconstructs analog input signal (54) by knowing from the prior training the effect of control unit (52) and the model of analog circuit (51).

Claims

1. A method for providing a digital output signal representing at least one analog input signal, comprising:

(a) feeding an analog circuit with said at least one analog input signal and a plurality of discrete correction signals;

(b) said analog circuit providing analog monitoring outputs,

wherein said at least one analog input signal and said discrete correction signals are jointly related by a relationship to said analog monitoring outputs, said relationship having an identification algorithm;

(c) receiving said analog monitoring outputs and a synchronization clock and implementing a negative feedback control loop by said feeding said analog circuit with said discrete correction signals, in order to keep at least one of said analog monitoring outputs to be within a previously defined constraint;

(d) identifying said relationship thereby creating an internal representation of said relationship;

(e) calculating said digital output signal by using a digital representation of said discrete correction signals and said internal representation, wherein said digital output signal represents said at least one analog input signal.

2. The method of claim 1, further comprising the step of, prior to said (a) feeding:

(f) training by inputting a plurality of known analog training signals into said analog circuit.

3. The method of claim 1, wherein said analog circuit is time varying according to said synchronization clock.

4. The method of claim 1, wherein said discrete correction signals are based on selectably either at least two previously defined values or at least two previously defined waveforms.

5. The method of claim 1, wherein said analog circuit is a linear analog circuit.

6. The method of claim 5 wherein said identifying includes a least-mean square (LMS) technique.

7. The method of claim 1, wherein said calculating is only up to a previously defined partial reconstruction of said at least one analog input signal.

8. The method of claim 1, wherein said identifying is repeated occasionally within a training period, and said identifying includes feeding at least one analog training signal during said training period.

9. The method of claim 8, wherein said at least one analog signal is produced by feeding known digital signals to a digital to analog converter, said known digital signals driving said at least one analog training signal.

10. The method of claim 8, where said identifying is performed in the background by interleaving said at least one analog input signal and said at least one analog training signal.

11. The method of claim 8, wherein said at least one analog training signal is produced by cascading said analog circuit with at least one additional analog circuit fed by a known reference signal and said identifying is of a relationship between said known reference signal and an output of said analog circuit.

12. The method of claim 1, wherein said identifying uses available statistical information about said at least one analog input signal.

13. The method of claim 1, wherein said analog circuit is a multi-stage analog circuit including a plurality of stages, the method further comprising the steps of:

(a) for each said stage, except the first stage, receiving as input signals at least one analog signal from a preceding stage and at least one discrete correction signal;

(b) the first stage receiving as inputs at least one discrete correction signal and at least one analog input signal;

(c) for each said stage, providing at least one analog monitoring output,

(d) providing, for each stage of the multi-stage analog circuit, said at least one discrete correction signal.

14. The method of claim 13, wherein operation of each stage is dependent on at least one other stage.

15. The method of claim 1, wherein at least one of said analog monitoring outputs is time continuous.

16. A multi-stage analog signals sampler, wherein each stage of the multi-stage analog signals sampler includes:

(a) an amplifier which amplifies an input analog signal, thereby producing an amplified analog signal;

(b) a capacitor which at least approximately integrates said amplified analog signal, thereby producing an integrated signal;

wherein a discharge mechanism discharges said capacitor; and

(c) a mechanism which performs a comparison of said integrated signal with at least one threshold, and adds at least one previously defined correction to said amplified analog signal, and registers an output of said comparison in a digital logic.

17. A multi-stage analog signals sampler, wherein each stage of said multi-stage analog signals sampler includes:

(a) an amplifier amplifying an analog input signal, thereby producing an amplified analog signal;

(b) a mechanism which renders said amplifier dependent on a synchronization clock;

(c) a circuit which features a time constant on the order of a period of said synchronization clock, wherein said circuit modifies said amplified analog signal;

(d) a mechanism which provides, at least one discrete correction signal to said analog input signal, by using information from at least one other said stage, wherein said at least one discrete correction signal performs a negative feedback control loop which controls said analog input signal; and

(e) a mechanism which receives and stores, a digital representation of said at least one discrete correction signal.

18. The multi-stage analog signals sampler, according to claim 17, further comprising

(f) a mechanism which identifies a relationship between said at least one discrete correction signal, said analog input signal and said information used in said negative feedback control loop of said multi-stage analog signals sampler,

(g) a digital signal processing mechanism which calculates a digital output signal representing said analog input signal.

19. A parallel analog signals sampler, comprising a plurality of the multi-stage analog signals samplers according to claim 17, wherein the respective digital representations of the multi-stage signal samplers are output to a common digital signal processing mechanism, the parallel analog signals sampler comprising a mechanism which identifies a joint relationship between a parallel input and the parallel output of said multi-stage analog signals samplers.

20. The parallel multi-stage analog signals sampler, according to claim 19, wherein said multi-stage analog signals samplers are placed in close proximity, wherein crosstalk between said parallel analog signal samplers is included in said joint model.