Command sequence for optimized power consumption

• US 7,305,514 B2
• Filed: 07/26/2006
• Issued: 12/04/2007
• Est. Priority Date: 05/28/2002
• Status: Expired due to Term

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Roohparvar, Frankie Fariborz
• Primary Examiner(s): Peugh; Brian R
• Assistant Examiner(s): Farrokh; Hashem
• Application Number:
  US11/493,127
• Publication Number:
  US 20060265564A1
• Time in Patent Office: 496 Days
• Field of Search: 711/103
• US Class Current: 711/103
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 2207/2227 Standby or low power modes
• CPC Class Codes: G11C 7/1078 Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
• CPC Class Codes: G11C 7/1084 Data input buffers, e.g. comprising level conversion circuits, circuits for adapting load
• CPC Class Codes: G11C 7/109 Control signal input circuits
• CPC Class Codes: G11C 7/22 Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management

Abstract

Power consumption by a memory device may be controlled by maintaining data input buffers in an off state until a command sequence containing a specified command is received by the memory. A software command sequence is provided to the memory device where the software command sequence was constructed by generating a command sequence including the specified command. The data input buffers are returned to an off state upon completion of a memory operation defined in the received command sequence.

Claims

1. A method comprising:

controlling a state of a data buffer in a memory such that the data buffer is placed in an on state in response to receiving a predetermined memory command in a sequence of memory commands, the data buffer placed in the on state during the sequence of memory commands before performing the memory operation, and such that the data buffer is placed in an off state in response to completion of a memory operation correlated to the sequence of memory commands.

2. The method of claim 1, wherein controlling a state of a data buffer in a memory such that the data buffer is placed in an on state in response to receiving a predetermined memory command includes controlling the state of the data buffer in the memory such that the data buffer is placed in the on state in response to receiving a write command.

3. The method of claim 1, wherein controlling a state of a data buffer in a memory such that the data buffer is placed in an on state in response to receiving a predetermined memory command includes controlling the state of the data buffer in the memory such that the data buffer is placed in the on state in response to concurrently receiving a write command and valid data.

4. The method of claim 1, wherein controlling the state of the data buffer in the memory includes controlling operations in the memory using a state machine.

5. The method of claim 1, wherein controlling a state of a data buffer in a memory includes arranging in a load command unit the predetermined memory command in the command sequence and sending the command sequence to the memory.

6. The method of claim 1, wherein controlling a state of a data buffer in a memory includes using a processor to control the state of the data buffer in the memory.

7. A method comprising:

controlling a state of a data buffer in a memory such that the data buffer is placed in an on state in response to receiving a predetermined memory command in a sequence of memory commands and such that the data buffer is placed in an off state in response to completion of a memory operation correlated to the sequence of memory commands, wherein controlling a state of a data buffer in a memory includes monitoring the sequence of memory commands in the memory using control circuitry in the memory.

8. The method of claim 7, wherein monitoring the sequence of memory commands in the memory using control circuitry in the memory includes monitoring a sequence of memory commands having between three and eight cycles in which to place the predetermined memory command.

9. A method comprising:

controlling a state of a data buffer in a memory such that the data buffer is placed in an on state in response to receiving a predetermined memory command in a sequence of memory commands and such that the data buffer is placed in an off state in response to completion of a memory operation correlated to the sequence of memory commands, wherein controlling a state of a data buffer in a memory includes arranging in a load command unit the predetermined memory command in the command sequence and sending the command sequence to the memory, wherein the method includes controlling the load command unit with a processor.

10. An apparatus comprising:

control circuitry to control a state of a data buffer in a memory, such that the data buffer is placed in an on state in response to receiving a predetermined memory command in a sequence of memory commands, the data buffer placed in the on state during the sequence of memory commands before performing the memory operation, and such that the data buffer is placed in an off state in response to completion of a memory operation correlated to the sequence of memory commands.

11. The apparatus of claim 10, wherein the control circuitry is disposed in the memory and coupled to the data buffer, the data input buffer switchable to the on state and responsive to the control circuitry detecting a write command in the sequence of memory commands generated external to the memory.

12. The apparatus of claim 11, wherein the apparatus includes a non-switchable data buffer to operate in the on state.

13. The apparatus of claim 10, wherein the control circuitry is arranged to generate the sequence of memory commands and to load the memory.

14. The apparatus of claim 13, wherein the control circuitry is disposed external to the memory.

15. The apparatus of claim 13, wherein the control circuitry is configured to receive a write request to initiate a memory operation.

16. The apparatus of claim 10, wherein the control circuitry is disposed in a processor external to the memory.

17. A machine readable medium that stores instructions, which when performed by a machine, cause the machine to:

control a state of a data buffer in a memory such that the data buffer is placed in an on state in response to receiving a predetermined memory command in a sequence of memory commands, the data buffer being placed in the on state during the sequence of memory commands before performing the memory operation, and such that the data buffer is placed in an off state in response to completion of a memory operation correlated to the sequence of memory commands.

18. The machine readable medium of claim 17, wherein the machine readable medium includes instructions to generate the sequence of memory commands and to load the memory.

19. The machine readable medium of claim 18, wherein the machine readable medium includes instructions to place the predetermined memory command in a predetermined cycle in the sequence of memory commands.

20. The machine readable medium of claim 18, wherein the predetermined memory command is a write command.

21. A method comprising:

forming a control circuit to control a state of a data buffer in a memory such that the data buffer is placed in an on state in response to receiving a predetermined memory command in a sequence of memory commands and the data buffer is placed in the on state during the sequence of memory commands before performing the memory operation, and such that the data buffer is placed in an off state in response to completion of a memory operation correlated to the sequence of memory commands.

22. The method of claim 21, wherein the method includes forming the control circuit in the memory and coupling the control circuit to the data buffer.

23. The method of claim 21, wherein the method includes coupling the control circuitry in the memory to address buffers in the memory.

24. The method of claim 21, wherein the method includes forming the control circuit in a load command unit and coupling an input to the control circuit, the input to receive a write request.

25. The method of claim 24, wherein the method includes coupling an output to the control circuit, the output to couple to the memory, the memory external to the load command unit.

26. The method of claim 21, wherein the method includes forming the control circuit in a processor.

27. The method of claim 26, wherein the method includes coupling the processor to the memory, the memory external to the processor.