Command sequence for optimized power consumption
First Claim
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1. A method comprising:
- controlling a state of a data buffer in a memory such that the data buffer is placed in an on state in response to receiving a predetermined memory command in a sequence of memory commands, the data buffer placed in the on state during the sequence of memory commands before performing the memory operation, and such that the data buffer is placed in an off state in response to completion of a memory operation correlated to the sequence of memory commands.
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Abstract
Power consumption by a memory device may be controlled by maintaining data input buffers in an off state until a command sequence containing a specified command is received by the memory. A software command sequence is provided to the memory device where the software command sequence was constructed by generating a command sequence including the specified command. The data input buffers are returned to an off state upon completion of a memory operation defined in the received command sequence.
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Citations
27 Claims
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1. A method comprising:
controlling a state of a data buffer in a memory such that the data buffer is placed in an on state in response to receiving a predetermined memory command in a sequence of memory commands, the data buffer placed in the on state during the sequence of memory commands before performing the memory operation, and such that the data buffer is placed in an off state in response to completion of a memory operation correlated to the sequence of memory commands. - View Dependent Claims (2, 3, 4, 5, 6)
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7. A method comprising:
controlling a state of a data buffer in a memory such that the data buffer is placed in an on state in response to receiving a predetermined memory command in a sequence of memory commands and such that the data buffer is placed in an off state in response to completion of a memory operation correlated to the sequence of memory commands, wherein controlling a state of a data buffer in a memory includes monitoring the sequence of memory commands in the memory using control circuitry in the memory. - View Dependent Claims (8)
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9. A method comprising:
controlling a state of a data buffer in a memory such that the data buffer is placed in an on state in response to receiving a predetermined memory command in a sequence of memory commands and such that the data buffer is placed in an off state in response to completion of a memory operation correlated to the sequence of memory commands, wherein controlling a state of a data buffer in a memory includes arranging in a load command unit the predetermined memory command in the command sequence and sending the command sequence to the memory, wherein the method includes controlling the load command unit with a processor.
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10. An apparatus comprising:
control circuitry to control a state of a data buffer in a memory, such that the data buffer is placed in an on state in response to receiving a predetermined memory command in a sequence of memory commands, the data buffer placed in the on state during the sequence of memory commands before performing the memory operation, and such that the data buffer is placed in an off state in response to completion of a memory operation correlated to the sequence of memory commands. - View Dependent Claims (11, 12, 13, 14, 15, 16)
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17. A machine readable medium that stores instructions, which when performed by a machine, cause the machine to:
control a state of a data buffer in a memory such that the data buffer is placed in an on state in response to receiving a predetermined memory command in a sequence of memory commands, the data buffer being placed in the on state during the sequence of memory commands before performing the memory operation, and such that the data buffer is placed in an off state in response to completion of a memory operation correlated to the sequence of memory commands. - View Dependent Claims (18, 19, 20)
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21. A method comprising:
forming a control circuit to control a state of a data buffer in a memory such that the data buffer is placed in an on state in response to receiving a predetermined memory command in a sequence of memory commands and the data buffer is placed in the on state during the sequence of memory commands before performing the memory operation, and such that the data buffer is placed in an off state in response to completion of a memory operation correlated to the sequence of memory commands. - View Dependent Claims (22, 23, 24, 25, 26, 27)
Specification