Methods and apparatus for accelerating data parsing
First Claim
Patent Images
1. XML accelerator parsing circuitry connected to a memory, the XML accelerator parsing circuitry comprising:
- white space handling subcircuitry configured to remove white space in an XML data string provided to the XML accelerator parsing circuitry;
hash calculation subcircuitry configured to calculate a hash value associated with the XML data string; and
duplication subcircuitry configured to copy the XML data string to permanent memory;
wherein the XML data string is simultaneously input to the white space handling subcircuitry, the hash calculation subcircuitry, and the duplication subcircuitry with a single access to each character in the XML data string,wherein the white space handling subcircuitry, the hash calculation subcircuitry, and the duplication subcircuitry simultaneously operate on a character in the XML data string.
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Abstract
According to the present invention, methods and apparatus are provided for improving the efficiency of data parsing. Data parsing can be applied to a variety of different types of data in various computer systems and appliances. Some of the methods and apparatus provided include techniques for scanning, verifying, calculating hash values, copying, and white space handling.
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Citations
18 Claims
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1. XML accelerator parsing circuitry connected to a memory, the XML accelerator parsing circuitry comprising:
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white space handling subcircuitry configured to remove white space in an XML data string provided to the XML accelerator parsing circuitry; hash calculation subcircuitry configured to calculate a hash value associated with the XML data string; and duplication subcircuitry configured to copy the XML data string to permanent memory; wherein the XML data string is simultaneously input to the white space handling subcircuitry, the hash calculation subcircuitry, and the duplication subcircuitry with a single access to each character in the XML data string, wherein the white space handling subcircuitry, the hash calculation subcircuitry, and the duplication subcircuitry simultaneously operate on a character in the XML data string.
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2. An integrated circuit for parsing Extensible Markup Language (XML) data, the integrated circuit comprising:
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memory; parsing circuitry configured to parse an element tag provided to the integrated circuit, wherein the parsing circuitry scans for characters associated with the element tag, wherein each of the characters is simultaneously input into a first component, a second component, and a third component of the parsing circuitry with a single access to the character, wherein the first component calculates a hash value for the input character, the second component copies the input character to a first preallocated block of memory, and the third component performs white space handling for the input character, wherein the first, second, and third components simultaneously perform the hash value calculation, the copying, and the white space handling while the scan of the characters occurs; and an interface for allowing communication between the parsing circuitry and memory. - View Dependent Claims (3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18)
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Specification