Membrane 3D IC fabrication

• US 7,307,020 B2
• Filed: 12/18/2003
• Issued: 12/11/2007
• Est. Priority Date: 04/08/1992
• Status: Expired due to Term

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: ELM TECHNOLOGY CORPORATION
• Inventors: Leedy, Glenn J
• Primary Examiner(s): Norton, Nadine G.
• Assistant Examiner(s): Umez-Eronini, Lynette T.
• Application Number:
  US10/742,057
• Publication Number:
  US 20040132303A1
• Time in Patent Office: 1,454 Days
• Field of Search: 438/689, 216/33, 298/31, 298/50, 298/52, 298/77
• US Class Current: 438/689
• CPC Class Codes: G02F 1/13452 Conductors connecting driver circuitry and terminals of panels
• CPC Class Codes: G02F 1/136281 having a transmissive semiconductor substrate
• CPC Class Codes: G03F 7/70658 Electrical testing
• CPC Class Codes: G11C 29/006 at wafer scale level, i.e. wafer scale integration [WSI]
• CPC Class Codes: H01L 21/762 Dielectric regions , e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
• CPC Class Codes: H01L 21/76264 SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
• CPC Class Codes: H01L 21/76289 Lateral isolation by air gap
• CPC Class Codes: H01L 21/764 Air gaps H01L21/76264 takes precedence
• CPC Class Codes: H01L 21/8221 Three dimensional integrated circuits stacked in different levels
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/05552 in top view
• CPC Class Codes: H01L 2224/0557 the external layer being disposed on a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/13009 Bump connector integrally formed with a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/16227 the bump connector connecting to a bond pad of the item
• CPC Class Codes: H01L 2224/80001 by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
• CPC Class Codes: H01L 23/538 the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates H05K takes precedence; manufacture or treatment H01L21/4846 ; mountings per se H01L23/12; materials H01L23/49866
• CPC Class Codes: H01L 23/5381 Crossover interconnections, e.g. bridge stepovers
• CPC Class Codes: H01L 23/5383 Multilayer substrates H01L23/5385 takes precedence; multilayer metallisation on monolayer substrates H01L23/538
• CPC Class Codes: H01L 23/5386 Geometry or layout of the interconnection structure
• CPC Class Codes: H01L 23/5387 : Flexible insulating substrates H01L23/5388 takes precedence
• CPC Class Codes: H01L 25/0652 : the devices being arranged next and on each other, i.e. mixed assemblies
• CPC Class Codes: H01L 25/0655 : the devices being arranged next to each other
• CPC Class Codes: H01L 25/50 : Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 27/0207 : Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00011 : Not relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/0002 : Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/01014 : Silicon [Si]
• CPC Class Codes: H01L 2924/01019 : Potassium [K]
• CPC Class Codes: H01L 2924/0102 : Calcium [Ca]
• CPC Class Codes: H01L 2924/01057 : Lanthanum [La]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/1305 : Bipolar Junction Transistor [BJT]
• CPC Class Codes: H01L 2924/13091 : Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/15153 : the die mounting substrate comprising a recess for hosting the device
• CPC Class Codes: H01L 2924/15165 : Monolayer substrate
• CPC Class Codes: H01L 2924/15312 : being a pin array, e.g. PGA
• CPC Class Codes: H01L 2924/3011 : Impedance
• CPC Class Codes: H01L 2924/3025 : Electromagnetic shielding
• CPC Class Codes: Y10S 148/135 : Removal of substrate
• CPC Class Codes: Y10S 438/928 : Front and rear surface processing
• CPC Class Codes: Y10S 438/938 : Lattice strain control or utilization
• CPC Class Codes: Y10S 438/942 : Masking
• CPC Class Codes: Y10S 438/967 : Semiconductor on specified insulator
• CPC Class Codes: Y10S 438/977 : Thinning or removal of substrate
• CPC Class Codes: Y10T 29/49128 : Assembling formed circuit to base
• CPC Class Codes: Y10T 29/49162 : by using wire as conductive path
• CPC Class Codes: Y10T 29/49165 : by forming conductive walled aperture in base
• CPC Class Codes: Y10T 29/49171 : with encapsulating
• CPC Class Codes: Y10T 29/4921 : with bonding

Abstract

General purpose methods for the fabrication of integrated circuits from flexible membranes formed of very thin low stress dielectric materials, such as silicon dioxide or silicon nitride, and semiconductor layers. Semiconductor devices are formed in a semiconductor layer of the membrane. The semiconductor membrane layer is initially formed from a substrate of standard thickness, and all but a thin surface layer of the substrate is then etched or polished away. In another version, the flexible membrane is used as support and electrical interconnect for conventional integrated circuit die bonded thereto, with the interconnect formed in multiple layers in the membrane. Multiple die can be connected to one such membrane, which is then packaged as a multi-chip module. Other applications are based on (circuit) membrane processing for bipolar and MOSFET transistor fabrication, low impedance conductor interconnecting fabrication, flat panel displays, maskless (direct write) lithography, and 3D IC fabrication.

Claims

1. A method of forming a stacked integrated circuit structure, comprising the steps of:

fabricating a first integrated circuit;

fabricating a second integrated circuit;

fabricating internal to at least one of the first and second integrated circuits a stress-controlled dielectric layer; and

bonding the first integrated circuit to the second integrated circuit to form said stacked integrated circuit structure with interconnects forming signal transmission paths between the first integrated circuit and the second integrated circuit.

2. The method of claim 1, wherein the stress-controlled dielectric layer is caused to have a stress of at least one of less than about 8×

10⁸ dynes/cm² and 2 to 100 times less than the fracture strength of the stress-controlled dielectric layer.

3. The method of claim 1, further comprising fabricating at least one of the first and second integrated circuits with an elastic dielectric layer.

4. The method of claim 3, wherein the elastic dielectric layer is caused to have a stress of at least one of less than about 8×

10⁸ dynes/cm² and 2 to 100 times less than the fracture strength of the elastic dielectric layer.

5. The method of claim 1, wherein the bonding further comprises using metal contact patterns for forming interconnects.

6. The method of claim 1, wherein the bonding further comprises thermal diffusion bonding the first integrated circuit and the second integrated circuit.

7. The method of claim 6, wherein the thermal diffusion bonding is one of metal-to-metal bonding and dielectric-to-dielectric bonding.

8. The method of claim 1, further comprising fabricating a barrier layer in at least one of the first and second substrates.

9. The method of claim 1, further comprising bonding said integrated circuit structure and a further substrate.

10. The method of claim 1, further comprising:

bonding said integrated circuit structure to at least one substrate with an integrated circuit formed thereon; and

forming interconnects between the integrated circuit of the at least one substrate and said integrated circuit structure.

11. The method of claim 2, wherein the stress is tensile.

12. The method of claim 4, wherein the stress is tensile.

13. The method of claim 1, wherein the stress-controlled dielectric layer is formed from at least one of an inorganic dielectric material and an organic dielectric material.

14. The method of claim 13, wherein the inorganic dielectric material is at least one of an oxide of silicon, a nitride of silicon, silicon dioxide and silicon nitride.

15. The method of claim 1, wherein the stress-controlled dielectric layer is caused to be at least one of elastic and substantially flexible.

16. The method of claim 3, wherein the elastic dielectric layer is caused to be substantially flexible.

17. The method of claim 1, further comprising forming the stress-controlled dielectric layer by depositing one or more stress-controlled dielectric films.

18. The method of claim 17, further comprising depositing at least one of the one or more stress-controlled dielectric films using at least one of multiple RF energy sources, Chemical Vapor Deposition, and Plasma Enhanced Chemical Vapor Deposition.

19. The method of claim 1, further comprising forming a plurality of interconnect conductors as a part of the stress-controlled dielectric layer, wherein the interconnect conductors are at least one of electrical and optical interconnect conductors.

20. The method of claim 1, wherein the stress-controlled dielectric layer is capable of forming at least one of a flexible membrane, an elastic membrane and a free standing membrane.

21. The method of claim 1, comprising forming the stress-controlled dielectric layer at a temperature of about 400°

C.

22. The method of claim 1, wherein the first integrated circuit is fabricated on a first substrate and the second integrated circuit is fabricated on a second substrate.

23. The method of claim 22, further comprising thinning at least one of the first and second substrates wherein at least one of the first and second integrated circuits is at least one of caused to be substantially flexible and able to be made substantially flexible while retaining its structural integrity.

24. The method of claim 22, further comprising thinning uniformly a major portion of at least one of the first substrate and the second substrate.

25. The method of claim 22, wherein at least some of the interconnects pass through at least one of the first and second substrates.

26. The method of claim 22, further comprising:

providing a principal surface on at least one of the first and second substrates; and

forming a barrier layer in at least one of the first and second substrates parallel to the principal surface of at least one of first and second substrates before fabricating at least one of the first and second integrated circuits, the principal surface of at least one of first and second substrates overlying the barrier layer of at least one of first and second substrates.

27. The method of claim 22, wherein at least one of the first and second substrates is thinned to less than about 50 microns.

28. The method of claim 22, wherein at least one of the first substrate and the second substrate is at least one of a semiconductor substrate, a silicon substrate, and a dielectric substrate.

29. The method of claim 1, wherein at least one of the first integrated circuit is fabricated on a first substrate, the second integrated circuit is fabricated on a second substrate, said integrated circuit structure is able to have a major portion of the first and second substrates removed throughout a full extent thereof while retaining its structural integrity, the bonding further comprises thermal diffusion bonding the first integrated circuit and the second integrated circuit, the substrates are at least one of a semiconductor substrate, a silicon wafer, and a dielectric substrate, at least one of the interconnects of said integrate circuit pass through at least one of the first and second substrates, the first integrated circuit is able to have a major portion of the first substrate removed throughout a full extent thereof while retaining its structural integrity, the second integrated circuit is able to have a major portion of the second substrate removed throughout a full extent thereof while retaining its structural integrity, the first integrated circuit is able to be thinned to about 50 microns or less throughout a full extent thereof while retaining its structural integrity, the second integrated circuit is able to be thinned to about 50 microns or less throughout a full extent thereof while retaining its structural integrity, the integrated circuit structure is caused to have a thickness of about 50 microns or less, the stress-controlled dielectric layer is caused to have at least one of a tensile stress and a stress of at least one of about 8×

10⁸ dynes/cm² or less and 2 to 100 times less than the fracture strength of the stress-controlled dielectric layer, the stress-controlled dielectric layer is caused to be at least one of elastic and substantially flexible, the stress-controlled dielectric layer is capable of forming a free standing membrane, the stress-controlled dielectric layer is formed from at least one of an inorganic dielectric material and an organic dielectric material with at least a major portion of the inorganic dielectric material formed from at least one of an oxide of silicon and a nitride of silicon, the stress-controlled dielectric layer is formed with at least one of electrical and optical interconnect conductors, and the stress-controlled dielectric layer is deposited using at least one of multiple RF energy sources, Chemical Vapor Deposition, and Plasma Enhanced Chemical Vapor Deposition.

30. A method of forming a stacked integrated circuit structure, comprising:

fabricating a first integrated circuit;

fabricating a second integrated circuit;

fabricating internal to at least one of the first and second integrated circuits a low stress dielectric layer;

bonding the first integrated circuit to the second integrated circuit; and

forming said stacked integrated circuit structure with interconnects forming signal transmission paths between the first integrated circuit and the second integrated circuit.

31. The method of claim 30, wherein the low stress dielectric layer is caused to have a stress of at least one of less than about 8×

10⁸ dynes/cm² and 2 to 100 times less than the fracture strength of the low stress dielectric layer.

32. The method of claim 30, further comprising fabricating at least one of the integrated circuits with an elastic dielectric layer.

33. The method of claim 32, wherein the elastic dielectric layer is caused to have a stress of at least one of less than about 8×

10⁸ dynes/cm² and 2 to 100 times less than the fracture strength of the elastic dielectric layer.

34. The method of claim 30, wherein the bonding further comprises using metal contact patterns for forming interconnects.

35. The method of claim 30, wherein the bonding further comprises thermal diffusion bonding the first integrated circuit and the second integrated circuit.

36. The method of claim 35, wherein the thermal diffusion bonding is one of metal-to-metal bonding and dielectric-to-dielectric bonding.

37. The method of claim 30, further comprising bonding said integrated circuit structure and a further substrate.

38. The method of claim 30, further comprising:

bonding said integrated circuit structure to at least one substrate with an integrated circuit formed thereon; and

forming interconnects between the integrated circuit of the at least one more substrate and said integrated circuit structure.

39. The method of claim 31, wherein the stress is tensile.

40. The method of claim 33, wherein the stress is tensile.

41. The method of claim 30, wherein the low stress dielectric layer is formed from at least one of an inorganic dielectric material and an organic dielectric material.

42. The method of claim 41, wherein the inorganic dielectric material is at least one of an oxide of silicon, a nitride of silicon, silicon dioxide and silicon nitride.

43. The method of claim 30, wherein the low stress dielectric layer is caused to be at least one of elastic and substantially flexible.

44. The method of claim 32, wherein the elastic dielectric layer is caused to be substantially flexible.

45. The method of claim 30, further comprising forming the low stress dielectric layer by depositing of one or more stress-controlled dielectric films.

46. The method of claim 45, further comprising depositing at least one of the one or more low stress dielectric films using at least one of multiple RF energy sources, Chemical Vapor Deposition, and Plasma Enhanced Chemical Vapor Deposition.

47. The method of claim 30, further comprising forming a plurality of interconnect conductors as a part of the low stress dielectric layer, wherein the interconnect conductors are at least one of electrical and optical interconnect conductors.

48. The method of claim 30, wherein the low stress dielectric layer is capable of forming at least one of a flexible membrane, an elastic membrane and a free standing membrane.

49. The method of claim 30, comprising forming the low stress dielectric layer at a temperature of about 400°

C.

50. The method of claim 30, wherein the first integrated circuit is fabricated on a first substrate and the second integrated circuit is fabricated on a second substrate.

51. The method of claim 50, further comprising thinning at least one of the first and second substrates wherein at least one of the first and second integrated circuits is at least one of caused to be substantially flexible and able to be made substantially flexible while retaining its structural integrity.

52. The method of claim 50, further comprising thinning uniformly a major portion of at least one of the first substrate and the second substrate.

53. The method of claim 50, wherein at least some of the interconnects pass through at least one of the first and second substrates.

54. The method of claim 50, further comprising fabricating a barrier layer in at least one of the first and second substrates.

55. The method of claim 50, further comprising:

providing a principal surface on at least one of the first and second substrates; and

forming a barrier layer in at least one of the first and second substrates parallel to the principal surface of at least one of the first and second substrates before fabricating at least one of the first and second integrated circuits, the principal surface of at least one of first and second substrates overlying the barrier layer of at least one of first and second substrates.

56. The method of claim 50, wherein at least one of the first and second substrates is thinned to less than about 50 microns.

57. The method of claim 50, wherein at least one of the first substrate and the second substrate is at least one of a semiconductor substrate, a silicon substrate, and a dielectric substrate.

58. The method of claim 30, wherein at least one of the first integrated circuit is fabricated on a first substrate, the second integrated circuit is fabricated on a second substrate, said integrated circuit structure is able to have a major portion of the first and second substrates removed throughout a full extent thereof while retaining its structural integrity, the bonding further comprises thermal diffusion bonding the first integrated circuit and the second integrated circuit, the substrates are at least one of a semiconductor substrate, a silicon wafer, and a dielectric substrate, at least one of the interconnects of said integrate circuit pass through at least one of the first and second substrates, the first integrated circuit is able to have a major portion of the first substrate removed throughout a full extent thereof while retaining its structural integrity, the second integrated circuit is able to have a major portion of the second substrate removed throughout a full extent thereof while retaining its structural integrity, the first integrated circuit is able to be thinned to about 50 microns or less throughout a full extent thereof while retaining its structural integrity, the second integrated circuit is able to be thinned to about 50 microns or less throughout a full extent thereof while retaining its structural integrity, the integrated circuit structure is caused to have a thickness of about 50 microns or less, the low stress dielectric layer is caused to have at least one of a tensile stress and a stress of at least one of about 8×

10⁸ dynes/cm² or less and 2 to 100 times less than the fracture strength of the low stress dielectric layer, the low stress dielectric layer is caused to be at least one of elastic and substantially flexible, the low stress dielectric layer is capable of forming a free standing membrane, the low stress dielectric layer is formed from at least one of an inorganic dielectric material and an organic dielectric material with at least a major portion of the inorganic dielectric material formed from at least one of an oxide of silicon and a nitride of silicon, the low stress dielectric layer is formed with at least one of electrical and optical interconnect conductors, and the low stress dielectric layer is deposited using at least one of multiple RF energy sources, Chemical Vapor Deposition, and Plasma Enhanced Chemical Vapor Deposition.

59. A method of forming a stacked integrated circuit structure, comprising:

fabricating a first integrated circuit;

fabricating a second integrated circuit on the first integrated circuit; and

fabricating internal to at least one of the first and second integrated circuits an elastic dielectric layer, with interconnects forming signal transmission paths between the first integrated circuit and the second integrated circuit.

60. The method of claim 59, wherein the elastic dielectric layer is caused to have a stress of at least one of less than about 8×

10⁸ dynes/cm² and 2 to 100 times less than the fracture strength of the elastic dielectric layer.

61. The method of claim 59, further comprising fabricating at least one of the first and second integrated circuits with a dielectric layer, wherein the dielectric layer is caused to have a stress of at least one of less than about 8×

10⁸ dynes/cm² and 2 to 100 times less than the fracture strength of the dielectric layer, and wherein the dielectric layer is caused to be at least one of elastic and substantially flexible.

62. The method of claim 59, further comprising fabricating a barrier layer in the substrate.

63. The method of claim 59, further comprising bonding of said integrated circuit structure and a further substrate.

64. The method of claim 59, further comprising:

bonding of said integrated circuit structure to at least one more substrate with an integrated circuit formed thereon; and

forming interconnects between the integrated circuit of the at least one more substrate and said integrated circuit structure.

65. The method of claim 60, wherein the stress is tensile.

66. The method of claim 61, wherein the stress is tensile.

67. The method of claim 59, wherein the elastic dielectric layer is formed from at least one of an inorganic dielectric material and an organic dielectric material.

68. The method of claim 67, wherein the inorganic dielectric material is at least one of an oxide of silicon, a nitride of silicon, silicon dioxide and silicon nitride.

69. The method of claim 59, wherein the elastic dielectric layer is caused to be substantially flexible.

70. The method of claim 59, further comprising forming the elastic dielectric layer by depositing one or more elastic dielectric films.

71. The method of claim 70, further comprising depositing at least one of the one or more elastic dielectric films using at least one of multiple RF energy sources, Chemical Vapor Deposition, and Plasma Enhanced Chemical Vapor Deposition.

72. The method of claim 59, further comprising forming a plurality of interconnect conductors as a part of the elastic dielectric layer, wherein the interconnect conductors are at least one of electrical and optical interconnect conductors.

73. The method of claim 59, wherein the elastic dielectric layer is capable of forming at least one of a flexible membrane, an elastic membrane and a free standing membrane.

74. The method of claim 59, comprising forming the elastic dielectric layer at a temperature of about 400°

C.

75. The method of claim 59, wherein the first integrated circuit is fabricated on a substrate.

76. The method of claim 75, further comprising thinning the substrate wherein the first and second integrated circuits are at least one of caused to be substantially flexible and able to be made substantially flexible while retaining its structural integrity.

77. The method of claim 75, further comprising thinning uniformly a major portion of the substrate.

78. The method of claim 75, further comprising:

providing a principal surface on the substrate; and

forming a barrier layer in the substrate parallel to the principal surface before fabricating the first and second integrated circuits, the principal surface overlying the barrier layer.

79. The method of claim 75, wherein the substrate is thinned to less than about 50 microns.

80. The method of claim 75, wherein the substrate is at least one of a semiconductor substrate, a silicon substrate, and a dielectric substrate.

81. The method of claim 59, wherein at least one of the first integrated circuit is fabricated on a substrate, said integrated circuit structure is able to have a major portion of the substrate removed throughout a full extent thereof while retaining its structural integrity, the substrate is at least one of a semiconductor substrate, a silicon wafer, and a dielectric substrate, the integrated circuit structure is able to have a major portion of the substrate removed throughout a full extent thereof while retaining its structural integrity, said integrated circuit structure is able to be thinned to about 50 microns or less throughout a full extent thereof while retaining its structural integrity, said integrated circuit structure is caused to have a thickness of about 50 microns or less, the elastic dielectric layer is caused to have at least one of a tensile stress and a stress of at least one of about 8×

10⁸ dynes/cm² or less and 2 to 100 times less than the fracture strength of the elastic dielectric layer, the elastic dielectric layer is caused to be at least one of elastic and substantially flexible, the elastic dielectric layer is capable of forming a free standing membrane, the elastic dielectric layer is formed from at least one of an inorganic dielectric material and an organic dielectric material with at least a major portion of the inorganic dielectric material formed from at least one of an oxide of silicon and a nitride of silicon, the elastic dielectric layer is formed with at least one of electrical and optical interconnect conductors, and the elastic dielectric layer is deposited using at least one of multiple RF energy sources, Chemical Vapor Deposition, and Plasma Enhanced Chemical Vapor Deposition.

82. A method of forming a stacked integrated circuit structure, comprising:

fabricating a first integrated circuit; and

fabricating a second integrated circuit on the first integrated circuit; and

fabricating internal to at least one of the first and second integrated circuits a dielectric layer wherein the dielectric layer is caused to have a stress of at least one of less than about 8×

10⁸ dynes/cm² and 2 to 100 times less than the fracture strength of the dielectric layer, with interconnects forming signal transmission paths between the first integrated circuit and the second integrated circuit.

83. The method of claim 82, wherein the dielectric layer is caused to be at least one of elastic and substantially flexible.

84. The method of claim 82, further comprising bonding of said integrated circuit and a further substrate.

85. The method of claim 82, further comprising:

bonding of said integrated circuit to at least one more substrate with an integrated circuit formed thereon; and

forming interconnects between the integrated circuit of the at least one more substrate and said integrated circuit.

86. The method of claim 82, wherein the stress is tensile.

87. The method of claim 82, wherein the dielectric layer is formed from at least one of an inorganic dielectric material and an organic dielectric material.

88. The method of claim 87, wherein the inorganic dielectric material is at least one of an oxide of silicon, a nitride of silicon, silicon dioxide and silicon nitride.

89. The method of claim 82, further comprising forming the dielectric layer by depositing one or more dielectric films.

90. The method of claim 89, further comprising depositing at least one of the one or more dielectric films using at least one of multiple RF energy sources, Chemical Vapor Deposition, and Plasma Enhanced Chemical Vapor Deposition.

91. The method of claim 82, further comprising forming a plurality of interconnect conductors as a part of the dielectric layer, wherein the interconnect conductors are at least one of electrical and optical interconnect conductors.

92. The method of claim 82, wherein the dielectric layer is capable of forming at least one of a flexible membrane, an elastic membrane and a free standing membrane.

93. The method of claim 82, comprising forming the dielectric layer at a temperature of about 400°

C.

94. The method of claim 82, wherein the first integrated circuit is fabricated on a substrate.

95. The method of claim 94, further comprising thinning the substrate wherein the first and second integrated circuits are at least one of caused to be substantially flexible and able to be made substantially flexible while retaining its structural integrity.

96. The method of claim 94, further comprising thinning uniformly a major portion of the substrate.

97. The method of claim 94, further comprising fabricating a barrier layer in the substrate.

98. The method of claim 94, further comprising:

providing a principal surface on the substrate; and

forming a barrier layer in the substrate parallel to the principal surface before fabricating the first and second integrated circuits, the principal surface overlying the barrier layer.

99. The method of claim 94, wherein the substrate is thinned to less than about 50 microns.

100. The method of claim 94, wherein the substrate is at least one of a semiconductor substrate, a silicon substrate, and a dielectric substrate.

101. The method of claim 82, wherein at least one of the first integrated circuit is fabricated on a substrate, said integrated circuit structure is able to have a major portion of the substrate removed throughout a full extent thereof while retaining its structural integrity, the substrate is at least one of a semiconductor substrate, a silicon wafer, and a dielectric substrate, said integrated circuit structure is able to have a major portion of the substrate removed throughout a full extent thereof while retaining its structural integrity, said 50 microns or less throughout a full extent thereof while retaining its structural integrity, said integrated circuit structure is caused to have a thickness of about 50 microns or less, the dielectric layer is caused to have a tensile stress, the dielectric layer is caused to be at least one of elastic and substantially flexible, the dielectric layer is capable of forming a free standing membrane, the dielectric layer is formed from at least one of an inorganic dielectric material and an organic dielectric material with at least a major portion of the inorganic dielectric material formed from at least one of an oxide of silicon and a nitride of silicon, the dielectric layer is formed with at least one of electrical and optical interconnect conductors, and the dielectric layer is deposited using at least one of multiple RF energy sources, Chemical Vapor Deposition, and Plasma Enhanced Chemical Vapor Deposition.

102. A method of forming a stacked integrated circuit structure, comprising:

fabricating a first integrated circuit;

fabricating a second integrated circuit;

fabricating internal to at least one of the first and second integrated circuits an elastic dielectric layer; and

bonding the first integrated circuit to the second integrated circuit to form said stacked integrated circuit structure with interconnects forming signal transmission paths between the first integrated circuit and the second integrated circuit.

103. The method of claim 102, wherein the elastic dielectric layer is caused to have a stress of at least one of less than about 8×

10⁸ dynes/cm² and 2 to 100 times less than the fracture strength of the elastic dielectric layer.

104. The method of claim 103, wherein the stress is tensile.

105. The method of claim 102, further comprising fabricating at least one of the first and second integrated circuits with an stress-controlled dielectric layer, wherein the stress-controlled dielectric layer is caused to be at least one of elastic and substantially flexible.

106. The method of claim 105, wherein the stress-controlled dielectric layer is caused to have a stress of at least one of less than about 8×

10⁸ dynes/cm² and 2 to 100 times less than the fracture strength of the stress-controlled dielectric layer.

107. The method of claim 106, wherein the stress is tensile.

108. The method of claim 102, wherein the bonding uses metal contact patterns for forming interconnects.

109. The method of claim 102, wherein the bonding further comprises thermal diffusion bonding the first integrated circuit and the second integrated circuit.

110. The method of claim 109, wherein the thermal diffusion bonding is one of metal-to-metal bonding and dielectric-to-dielectric bonding.

111. The method of claim 102, further comprising bonding of said integrated circuit structure and a further substrate.

112. The method of claim 102, further comprising:

bonding said integrated circuit structure to at least one more substrate with an integrated circuit formed thereon; and

forming interconnects between the integrated circuit of the at least one more substrate and said integrated circuit structure.

113. The method of claim 102, further comprising thinning at least one of the first and second substrates wherein said integrated circuit structure is able to be made substantially flexible while retaining its structural integrity.

114. The method of claim 102, wherein the elastic dielectric layer is formed from at least one of an inorganic dielectric material and an organic dielectric material.

115. The method of claim 114, wherein the inorganic dielectric material is at least one of an oxide of silicon, a nitride of silicon, silicon dioxide and silicon nitride.

116. The method of claim 102, wherein the elastic dielectric layer is caused to be substantially flexible.

117. The method of claim 102, further comprising forming the elastic dielectric layer by depositing one or more elastic dielectric films.

118. The method of claim 117, further comprising depositing at least one of the one or more elastic dielectric films using at least one of multiple RF energy sources, Chemical Vapor Deposition, and Plasma Enhanced Chemical Vapor Deposition.

119. The method of claim 102, further comprising forming a plurality of interconnect conductors as a part of the elastic dielectric layer, wherein the interconnect conductors are at least one of electrical and optical interconnect conductors.

120. The method of claim 102, wherein the elastic dielectric layer is capable of forming at least one of a flexible membrane, an elastic membrane and a free standing membrane.

121. The method of claim 102, comprising forming the elastic dielectric layer at a temperature of about 400°

C.

122. The method of claim 102, wherein the first integrated circuit is fabricated on a first substrate and the second integrated circuit is fabricated on a second substrate.

123. The method of claim 122, further comprising thinning at least one of the first and second substrates wherein at least one of the first and second integrated circuits is at least one of caused to be substantially flexible and able to be made substantially flexible while retaining its structural integrity.

124. The method of claim 122, further comprising thinning uniformly a major portion of at least one of the first substrate and the second substrate.

125. The method of claim 122, wherein at least one of the first and second substrates is thinned to less than about 50 microns.

126. The method of claim 122, wherein at least some of the interconnects pass through at least one of the first and second substrates.

127. The method of claim 122, further comprising fabricating a barrier layer in at least one of the first and second substrates.

128. The method of claim 122, further comprising:

providing a principal surface on at least one of the first and second substrates; and

forming a barrier layer in at least one of the first and second substrates parallel to the principal surface of at least one of the first and second substrates before fabricating at least one of the first and second integrated circuits, the principal surface of at least one of the first and second substrates overlying the barrier layer of at least one of the first and second substrates.

129. The method of claim 122, wherein at least one of the first substrate and the second substrate is at least one of a semiconductor substrate, a silicon substrate, and a dielectric substrate.

130. The method of claim 102, wherein at least one of the first integrated circuit is fabricated on a first substrate, the second integrated circuit is fabricated on a second substrate, said integrated circuit structure is able to have a major portion of the first and second substrates removed throughout a full extent thereof while retaining its structural integrity, the bonding further comprises thermal diffusion bonding the first integrated circuit and the second integrated circuit, the substrates are at least one of a semiconductor substrate, a silicon wafer, and a dielectric substrate, at least one of the interconnects of said integrate circuit pass through at least one of the first and second substrates, the first integrated circuit is able to have a major portion of the first substrate removed throughout a full extent thereof while retaining its structural integrity, the second integrated circuit is able to have a major portion of the second substrate removed throughout a full extent thereof while retaining its structural integrity, the first integrated circuit is able to be thinned to about 50 microns or less throughout a full extent thereof while retaining its structural integrity, the second integrated circuit is able to be thinned to about 50 microns or less throughout a full extent thereof while retaining its structural integrity, the integrated circuit structure is caused to have a thickness of about 50 microns or less, the elastic dielectric layer is caused to have at least one of a tensile stress and a stress of at least one of about 8×

10⁸ dynes/cm² or less and 2 to 100 times less than the fracture strength of the elastic dielectric layer, the elastic dielectric layer is caused to be at least one of elastic and substantially flexible, the elastic dielectric layer is capable of forming a free standing membrane, the elastic dielectric layer is formed from at least one of an inorganic dielectric material and an organic dielectric material with at least a major portion of the inorganic dielectric material formed from at least one of an oxide of silicon and a nitride of silicon, the elastic dielectric layer is formed with at least one of electrical and optical interconnect conductors, and the elastic dielectric layer is deposited using at least one of multiple RF energy sources, Chemical Vapor Deposition, and Plasma Enhanced Chemical Vapor Deposition.

131. A method of forming a stacked integrated circuit structure, comprising:

fabricating a first integrated circuit;

fabricating a second integrated circuit;

fabricating internal to at least one of the first and second integrated circuits an elastic dielectric layer;

bonding the first integrated circuit to the second integrated circuit; and

forming said stacked integrated circuit structure with interconnects forming signal transmission paths between the first integrated circuit and the second integrated circuit.

132. The method of claim 131, wherein the elastic dielectric layer is caused to have a stress of at least one of less than about 8×

10⁸ dynes/cm² and 2 to 100 times less than the fracture strength of the elastic dielectric layer.

133. The method of claim 132, wherein the stress is tensile.

134. The method of claim 131, further comprising fabricating at least one of the first and second integrated circuits with a low stress dielectric layer, wherein the low stress dielectric layer is caused to be at least one of elastic and substantially flexible.

135. The method of claim 134, wherein the low stress dielectric layer is caused to have a stress of at least one of less than about 8×

10⁸ dynes/cm² and 2 to 100 times less than the fracture strength of the low stress dielectric layer.

136. The method of claim 135, wherein the stress is tensile.

137. The method of claim 131, wherein the bonding further comprises using metal contact patterns for forming interconnects.

138. The method of claim 131, wherein the bonding further comprises thermal diffusion bonding the first integrated circuit and the second integrated circuit.

139. The method of claim 138, wherein the thermal diffusion bonding is one of metal-to-metal bonding and dielectric-to-dielectric bonding.

140. The method of claim 131, further comprising fabricating a barrier layer in at least one of the first and second substrates.

141. The method of claim 131, further comprising bonding said integrated circuit and a further substrate.

142. The method of claim 131, further comprising:

bonding said integrated circuit structure to at least one more substrate with an integrated circuit formed thereon; and

forming interconnects between the integrated circuit of the at least one more substrate and said integrated circuit structure.

143. The method of claim 131, wherein the elastic dielectric layer is formed from at least one of an inorganic dielectric material and an organic dielectric material.

144. The method of claim 143, wherein the inorganic dielectric material is at least one of an oxide of silicon, a nitride of silicon, silicon dioxide and silicon nitride.

145. The method of claim 131, wherein the elastic dielectric layer is caused to be substantially flexible.

146. The method of claim 131, further comprising forming the elastic dielectric layer by depositing one or more elastic dielectric films.

147. The method of claim 146, further comprising depositing at least one of the one or more elastic dielectric films using at least one of multiple RF energy sources, Chemical Vapor Deposition, and Plasma Enhanced Chemical Vapor Deposition.

148. The method of claim 131, further comprising forming a plurality of interconnect conductors as a part of the elastic dielectric layer, wherein the interconnect conductors are at least one of electrical and optical interconnect conductors.

149. The method of claim 131, wherein the elastic dielectric layer is capable of forming at least one of a flexible membrane, an elastic membrane and a free standing membrane.

150. The method of claim 131, comprising forming the elastic dielectric layer at a temperature of about 400°

C.

151. The method of claim 131, wherein the first integrated circuit is fabricated on a first substrate and the second integrated circuit is fabricated on a second substrate.

152. The method of claim 151, further comprising thinning at least one of the first and second substrates wherein at least one of the first and second integrated circuits is at least one of caused to be substantially flexible and able to be made substantially flexible while retaining its structural integrity.

153. The method of claim 151, further comprising thinning uniformly a major portion of at least one of the first substrate and the second substrate.

154. The method of claim 151, wherein the at least one of the first and second substrates is thinned to less than about 50 microns.

155. The method of claim 151, wherein at least some of the interconnects pass through at least one of the first and second substrates.

156. The method of claim 151, further comprising:

providing a principal surface on at least one of the first and second substrates; and

forming a barrier layer in at least one of the first and second substrates parallel to the principal surface of at least one of the first and second substrates before fabricating at least one of the first and second integrated circuits, the principal surface of at least one of the first and second substrates overlying the barrier layer of at least one of the first and second substrates.

157. The method of claim 151, wherein at least one of the first substrate and the second substrate is at least one of a semiconductor substrate, a silicon substrate, and a dielectric substrate.

158. The method of claim 131, wherein at least one of the first integrated circuit is fabricated on a first substrate, the second integrated circuit is fabricated on a second substrate, said integrated circuit structure is able to have a major portion of the first and second substrates removed throughout a full extent thereof while retaining its structural integrity, the bonding further comprises thermal diffusion bonding the first integrated circuit and the second integrated circuit, the substrates are at least one of a semiconductor substrate, a silicon wafer, and a dielectric substrate, at least one of the interconnects of said integrate circuit pass through at least one of the first and second substrates, the first integrated circuit is able to have a major portion of the first substrate removed throughout a full extent thereof while retaining its structural integrity, the second integrated circuit is able to have a major portion of the second substrate removed throughout a full extent thereof while retaining its structural integrity, the first integrated circuit is able to be thinned to about 50 microns or less throughout a full extent thereof while retaining its structural integrity, the second integrated circuit is able to be thinned to about 50 microns or less throughout a full extent thereof while retaining its structural integrity, the integrated circuit structure is caused to have a thickness of about 50 microns or less, the elastic dielectric layer is caused to have at least one of a tensile stress and a stress of at least one of about 8×

10⁸ dynes/cm² or less and 2 to 100 times less than the fracture strength of the elastic dielectric layer, the elastic dielectric layer is caused to be at least one of elastic and substantially flexible, the elastic dielectric layer is capable of forming a free standing membrane, the elastic dielectric layer is formed from at least one of an inorganic dielectric material and an organic dielectric material with at least a major portion of the inorganic dielectric material formed from at least one of an oxide of silicon and a nitride of silicon, the elastic dielectric layer is formed with at least one of electrical and optical interconnect conductors, and the elastic dielectric layer is deposited using at least one of multiple RF energy sources, Chemical Vapor Deposition, and Plasma Enhanced Chemical Vapor Deposition.