Intelligent probe card architecture

• US 7,307,433 B2
• Filed: 04/21/2004
• Issued: 12/11/2007
• Est. Priority Date: 04/21/2004
• Status: Active Grant

• Current Assignee: FormFactor Incorporated
• Original Assignee: FormFactor Incorporated
• Inventors: Miller, Charles A., Henson, Roy J., Chraft, Matthew E.
• Primary Examiner(s): PATEL, PARESH H
• Application Number:
  US10/828,755
• Publication Number:
  US 20050237073A1
• Time in Patent Office: 1,329 Days
• Field of Search: 324/754, 324/765, 324/758, 324/158.1, 324/72.5, 438/14, 438/17, 438/18, 714/719, 714/720, 439/482, 439/700
• US Class Current: 324/756.03
• CPC Class Codes: G01R 1/07385 using switching of signals between probe tips and test bed, i.e. the standard contact matrix which in its turn connects to the tester
• CPC Class Codes: G01R 1/36 Overload-protection arrangements or circuits for electric measuring instruments
• CPC Class Codes: G01R 31/2889 Interfaces, e.g. between probe and tester G01R31/31905 and G01R1/07364 take precedence
• CPC Class Codes: G01R 31/31905 Interface with the device under test [DUT], e.g. arrangements between the test head and the DUT, mechanical aspects, fixture
• CPC Class Codes: G01R 35/00 Testing or calibrating of apparatus covered by the other groups of this subclass

Abstract

A probe card for a wafer test system is provided with a number of on board features enabling fan out of a test system controller channel to test multiple DUTs on a wafer, while limiting undesirable effects of fan out on test results. On board features of the probe card include one or more of the following: (a) DUT signal isolation provided by placing resistors in series with each DUT input to isolate failed DUTs; (b) DUT power isolation provided by switches, current limiters, or regulators in series with each DUT power pin to isolate the power supply from failed DUTs; (c) self test provided using an on board micro-controller or FPGA; (d) stacked daughter cards provided as part of the probe card to accommodate the additional on board test circuitry; and (e) use of a interface bus between a base PCB and daughter cards of the probe card, or the test system controller to minimize the number of interface wires between the base PCB and daughter cards or between the base PCB and the test system controller.

Claims

1. A probe card assembly comprising:

a serial signal interface configured to connect to a test system controller;

a serial digital to analog converter configured to receive through the serial signal interface digital first test signals in serial from the test system controller, convert the first test signals to parallel, and provide the first test signals to a plurality of first test probes in analog form, wherein the first test probes are configured to contact ones of a plurality of electronic devices under test; and

a parallel analog to digital converter configured to receive analog response signals in parallel from second test probes configured to contact ones of the electronic devices under test, convert the response signals to serial, and provide the response signals through the serial signal interface in digital form to the test system controller.

2. The probe card assembly of claim 1 comprising:

a space transformer supporting the first test probes and the second test probes;

at least one daughter card; and

a base PCB electrically interconnected with the space transformer and the at least one daughter card, wherein the serial digital to analog converter and the parallel analog to digital converter are each provided on at least one of the space transformer, the base PCB, and the at least one daughter card.

3. The probe card assembly of claim 1 further comprising a parallel signal interface configured to receive in parallel from the test system controller third test signals.

4. The probe card assembly of claim 1 further comprising a signal connection configured to receive a second test signal from the test system controller and distribute the second test signal to a plurality of third test probes, wherein each of the third test probes is configured to contact a different one of the devices under test.

5. The probe card assembly of claim 4 further comprising a switching circuit configured to select for connection to the test system controller any one of a plurality of fourth test probes configured to contact a different one of the devices under test.