Integrated circuit output driver circuitry with programmable preemphasis

• US 7,307,446 B1
• Filed: 08/24/2006
• Issued: 12/11/2007
• Est. Priority Date: 01/07/2003
• Status: Expired due to Fees

• Current Assignee: Altera Corporation (Intel Corporation)
• Original Assignee: Altera Corporation (Intel Corporation)
• Inventors: Shumarayev, Sergey Y., White, Thomas H., Patel, Rakesh H., Wong, Wilson
• Primary Examiner(s): Tan, Vibol
• Application Number:
  US11/510,514
• Time in Patent Office: 474 Days
• Field of Search: 326/115, 326/121, 326/127, 327/108
• US Class Current: 326/26
• CPC Class Codes: H03K 19/018585 programmable
• CPC Class Codes: H03K 2005/00032 Dc control of switching transistors
• CPC Class Codes: H03K 2005/00065 by current control, e.g. by parallel current control transistors
• CPC Class Codes: H03K 5/06 by the use of delay lines or other analogue delay elements
• CPC Class Codes: H03K 5/13 Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
• CPC Class Codes: H03K 5/151 with two complementary outputs

Abstract

Programmable logic device integrated circuitry having differential I/O circuitry is provided. The differential I/O circuitry may include output drivers for providing differential digital output data signals across pairs of output lines. A user may program the I/O circuitry to accommodate different high-speed differential I/O signaling standards. The user may also program the I/O circuitry to provide a desired amount of preemphasis to the output data signals.

Claims

1. Preemphasis circuitry for providing preemphasis to differential digital output data signals, comprising:

programmable pulse generator circuitry that is programmable to control duration of the preemphasis;

programmable current supply circuitry that is programmable to control magnitude of preemphasis; and

preemphasis driver circuitry coupled to the programmable pulse generator circuitry and the programmable current supply circuitry for producing the preemphasis, wherein the programmable pulse generator circuitry further comprises a function control element that is programmable to control duration of the preemphasis.

2. The preemphasis circuitry of claim 1, wherein the programmable pulse generator circuitry comprises a delay circuit that is programmable to control duration of the preemphasis.

3. The preemphasis circuitry of claim 1, wherein the programmable pulse generator circuitry comprises a pulse generator.

4. The preemphasis circuitry of claim 1, wherein the programmable current supply circuitry comprises a function control element that is programmable to control magnitude of preemphasis.

5. The preemphasis circuitry of claim 1, wherein the preemphasis circuitry is adapted to provide preemphasis for different high-speed differential I/O signaling standards.

6. The preemphasis circuitry of claim 5, wherein the different high-speed differential I/O signaling standards include at least one signaling standard selected from the group of standards consisting of LVPECL, LVDS, and PCML.

7. A programmable logic device integrated circuit comprising:

main differential driver circuitry for producing differential digital output data signals across a pair of output lines; and

the preemphasis circuitry of claim 1 for providing preemphasis to the differential digital output data signals.

8. Preemphasis circuitry for providing preemphasis to differential digital output data signals, comprising:

programmable pulse generator circuitry that is programmable to control duration of the preemphasis;

programmable current supply circuitry that is programmable to control magnitude of preemphasis;

preemphasis driver circuitry coupled to the programmable pulse generator circuitry and the programmable current supply circuitry for producing the preemphasis; and

programmable circuitry that is programmable to control provision of slope steepening by the preemphasis driver circuitry.

9. Preemphasis circuitry for providing preemphasis to differential digital output data signals, comprising:

programmable current supply circuitry, wherein the magnitude of preemphasis is controllable by the programmable current supply circuitry;

preemphasis driver circuitry coupled to the programmable current supply circuitry for producing the preemphasis; and

programmable pulse generator circuitry coupled to the preemphasis driver circuitry that is programmable to control duration of the preemphasis, wherein the programmable pulse generator circuitry further comprises a function control element that is programmable to control duration of the preemphasis.

10. The preemphasis circuitry of claim 9, wherein the programmable pulse generator circuitry comprises a delay circuit that is programmable to control duration of the preemphasis.

11. The preemphasis circuitry of claim 9, wherein the programmable pulse generator circuitry comprises a pulse generator.

12. The preemphasis circuitry of claim 9, wherein the programmable current supply circuitry comprises a function control element that is programmable to control magnitude of the preemphasis.

13. The preemphasis circuitry of claim 9, wherein the preemphasis circuitry is adapted to provide preemphasis for different high-speed differential I/O signaling standards.

14. The preemphasis circuitry of claim 9, wherein the different high-speed differential I/O signaling standards include at least one signaling standard selected from the group of standards consisting of LVPECL, LVDS, and PCML.

15. A programmable logic device integrated circuit comprising:

main differential driver circuitry for producing differential digital output data signals across a pair of output lines; and

the preemphasis circuitry of claim 9 for providing preemphasis to the differential digital output data signals.

16. Preemphasis circuitry for providing preemphasis to differential digital output data signals, comprising:

programmable current supply circuitry, wherein the magnitude of preemphasis is controllable by the programmable current supply circuitry;

preemphasis driver circuitry coupled to the programmable current supply circuitry for producing the preemphasis; and

programmable circuitry that is programmable to control provision of slope steepening by the preemphasis driver circuitry.