Automatic status assignment logic circuit apparatus for bay devices
First Claim
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1. An automatic assignment logical circuit apparatus for selecting a master device and a slave device from among a first bay device and a second bay device, wherein said first bay device being connected to the first bay connector and said second bay device being connected to the second bay connector, and said first bay connector and said second bay connector are in cascaded, said automatic assignment logical circuit apparatus comprising:
- an OR gate having first and second connection points for electrically connecting to said first bay connector, wherein said first and second connection points for receiving a pair of Boolean algebra value from said first bay connector and output a first Boolean algebra value;
a first transistor having a emitter electrode for receiving said first Boolean algebra value and having base electrode for electrically connecting to said first bay connector and a reference voltage also applied to said base electrode, wherein said first transistor will be conducted when a device is plugged into said first bay connector to trigger said base electrode and said base electrode will not be triggered when a device is pulled out said first bay connector;
a second transistor having a base electrode for receiving said first Boolean algebra value passed through said first transistor and a collector electrode for electrically connecting to said first bay connector, wherein said second transistor will be conducted when said first Boolean algebra value having high level and generates a second Boolean algebra value at said collector electrode for sending to said first bay connector and a high voltage also applied to said collector electrode; and
a third transistor having a base electrode for receiving said second Boolean algebra value passing through said second transistor and generating a third Boolean algebra value at said third transistor'"'"'s collector electrode which is electrically connected to said second bay connector, wherein said third transistor will be conducted when said second Boolean algebra value having high level and said generated third Boolean algebra value for sending to said second bay connector and a high voltage also applied to said collector electrode.
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Abstract
In accordance with the present invention, the circuit apparatus has a first and a second connection point each for respectively connecting to the first bay and second bay for communicating with them to determine which device in the bays is the master device. The circuit apparatus also has a third and a fourth connection point both of them for connecting to the first bay or second bay for receiving the Boolean algebra to determine which device is the master device. The circuit apparatus further has a fifth connection point for determining whether the circuit apparatus works.
11 Citations
10 Claims
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1. An automatic assignment logical circuit apparatus for selecting a master device and a slave device from among a first bay device and a second bay device, wherein said first bay device being connected to the first bay connector and said second bay device being connected to the second bay connector, and said first bay connector and said second bay connector are in cascaded, said automatic assignment logical circuit apparatus comprising:
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an OR gate having first and second connection points for electrically connecting to said first bay connector, wherein said first and second connection points for receiving a pair of Boolean algebra value from said first bay connector and output a first Boolean algebra value; a first transistor having a emitter electrode for receiving said first Boolean algebra value and having base electrode for electrically connecting to said first bay connector and a reference voltage also applied to said base electrode, wherein said first transistor will be conducted when a device is plugged into said first bay connector to trigger said base electrode and said base electrode will not be triggered when a device is pulled out said first bay connector; a second transistor having a base electrode for receiving said first Boolean algebra value passed through said first transistor and a collector electrode for electrically connecting to said first bay connector, wherein said second transistor will be conducted when said first Boolean algebra value having high level and generates a second Boolean algebra value at said collector electrode for sending to said first bay connector and a high voltage also applied to said collector electrode; and a third transistor having a base electrode for receiving said second Boolean algebra value passing through said second transistor and generating a third Boolean algebra value at said third transistor'"'"'s collector electrode which is electrically connected to said second bay connector, wherein said third transistor will be conducted when said second Boolean algebra value having high level and said generated third Boolean algebra value for sending to said second bay connector and a high voltage also applied to said collector electrode. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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Specification
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Current AssigneeQuanta Computer
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Original AssigneeQuanta Computer
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InventorsYu, Chen-Yo, Wu, Chun-Hsien
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Primary Examiner(s)Cho, James H.
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Application NumberUS11/439,125Publication NumberTime in Patent Office566 DaysField of Search326/75, 326/82, 326/89, 326 90- 91US Class Current326/89CPC Class CodesG06F 13/385 for adaptation of a particu...
