System and method for adaptive duty cycle optimization

• US 7,307,461 B2
• Filed: 09/12/2003
• Issued: 12/11/2007
• Est. Priority Date: 09/12/2003
• Status: Expired due to Fees

• Current Assignee: Rambus Inc.
• Original Assignee: Rambus Inc.
• Inventors: Nguyen, Huy, Yu, Leung, Lau, Benedict, Vu, Roxanne
• Primary Examiner(s): Lam; Tuan T.
• Assistant Examiner(s): Nguyen; Hiep
• Application Number:
  US10/661,225
• Publication Number:
  US 20050058233A1
• Time in Patent Office: 1,551 Days
• Field of Search: 327/175, 327/18, 327/20, 327/26
• US Class Current: 327/172
• CPC Class Codes: G11C 7/1078 Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
• CPC Class Codes: G11C 7/1093 Input synchronization
• CPC Class Codes: G11C 7/22 Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
• CPC Class Codes: G11C 7/222 Clock generating, synchronizing or distributing circuits within memory device

Abstract

A system and method for configuring a receiver such that the duty cycle of the receiver clock accurately matches the duty cycle of the data signal received. This adaptive system and method calibrates a receiver'"'"'s duty cycle to optimize the receiver timing margin for different data signal types and different slave devices. In one embodiment, a duty cycle correction circuit matches the receiver clock to a predetermined duty cycle. The receiver clock is then configured to have a duty cycle skewed from the predetermined duty cycle based on the specific data signal received. In a receiver system utilizing a clock tree, individual branches of the clock tree are configured to have respective duty cycles skewed to match the duty cycle of a data signal received from a specific transmitting device.

Claims

1. A method of adjusting a receiver clock duty cycle, comprising:

receiving a system clock signal;

detecting a duty cycle of a data signal;

comparing the detected duty cycle of the data signal with a predetermined duty cycle in order to determine a first difference between the detected data signal duty cycle and the predetermined duty cycle;

generating a receiver clock from the system clock signal; and

adjusting a duty cycle of the receiver clock in accordance with the first difference between the detected data signal duty cycle and the predetermined duty cycle.

2. The method of claim 1, wherein detecting the duty cycle of a data signal comprises the detecting a first duty cycle of a first data signal from a first device, and detecting a second duty cycle of a second data signal from a second device;

comparing the detected duty cycle of the data signal with a predetermined duty cycle comprises comparing the first duty cycle with a first predetermined duty cycle in order to determine a first difference between the first duty cycle and the first predetermined duty cycle, and comparing the second duty cycle with a second predetermined duty cycle in order to determine a second difference between the second duty cycle and the second predetermined duty cycle; and

adjusting a duty cycle of the receiver clock comprises adjusting a duty cycle of the receiver clock in accordance with the first difference when a receiver receives a data signal from the first device and adjusting the duty cycle of the receiver clock in accordance with the second difference when the receiver receives a data signal from the second device.

3. The method of claim 2, wherein the first and second data signals have signaling types which are different.

4. The method of claim 3, wherein the first and second predetermined duty cycles are different.

5. The method of claim 2, wherein the first and second devices are located on different integrated circuits.

6. The method of claim 1, including

detecting a duty cycle of the system clock signal;

comparing the duty cycle of the system clock signal with the predetermined duty cycle in order to determine a third difference between the detected system clock signal duty cycle and the predetermined duty cycle; and

adjusting the duty cycle of the receiver clock in accordance with the third difference.

7. The method of claim 6, wherein the third difference is less than about 10% of the predetermined duty cycle.

8. The method of claim 6, wherein the adjusting includes adjusting the duty cycle of the receiver clock such that a difference between the duty cycle of the receiver clock and the predetermined duty cycle is less than the third difference.

9. The method of claim 6, wherein the adjusting includes generating a duty cycle correction value based on the third difference and applying the duty cycle correction value to an amplifier circuit configured to alter the receiver clock signal duty cycle based on the duty cycle correction value.

10. The method of claim 9, wherein the duty cycle correction value determines which transistors are turned on in a binary-weighted set of transistors.

11. The method of claim 9, wherein the duty cycle correction value determines a voltage applied to a gate in a duty cycle correction circuit within the amplifier.

12. The method of claim 1, including processing the data signal using the duty cycle of the adjusted receiver clock.

13. The method of claim 1, wherein the predetermined duty cycle is 50%.

14. The method of claim 1, wherein the adjusting includes adjusting the duty cycle of the receiver clock such that a difference between the duty cycle of the receiver clock and the detected duty cycle of the data signal is less than the first difference.

15. The method of claim 1, wherein the adjusting includes generating a skew value based on the first difference and storing the skew value in a register.

16. The method of claim 15, further comprising applying the skew value to an amplifier circuit configured to alter the receiver clock signal duty cycle based on the skew value.

17. The method of claim 16, wherein the skew value determines which transistors are turned on in a binary-weighted set of transistors.

18. The method of claim 1, wherein the first difference is less than about 10% of the predetermined duty cycle.

19. The method of claim 1, wherein the method is performed by an integrated circuit and the data signal is received from a module with the integrated circuit.

20. The method of claim 1, wherein the method is performed by a first integrated circuit and the data signal is received from another integrated circuit.

21. An integrated circuit, comprising:

a clock receiver configured to receive a system clock signal having a duty cycle;

a data signal duty cycle detector configured to detect a first duty cycle of a first data signal and to generate a first difference signal representing a difference between the first duty cycle and a first predetermined duty cycle; and

a receiver clock generator configured to output a receiver clock signal based on the system clock signal and the first difference signal, the receiver clock generator including a one or more correction circuits configured to adjust a duty cycle of the receiver clock signal in accordance with the first difference signal.

22. The integrated circuit of claim 21, wherein the data signal duty cycle detector is further configured to detect a second duty cycle of a second data signal and to generate a second difference signal representing a difference between the second data signal duty cycle and a second predetermined duty cycle;

the first data signal has a first data signal type, the second data signal has a second data signal type, and the receiver clock generator is further configured to output a first receiver clock signal based on the system clock signal and the first difference signal when a receiver receives a data signal of the first data signal type and to output a second receiver clock signal based on the system clock signal and the second difference signal when the receiver receivers a data signal of the second data signal type.

23. The integrated circuit of claim 22, wherein the first and second data signaling types are different.

24. The integrated circuit of claim 23, wherein the first and second predetermined duty cycles are different.

25. The integrated circuit of claim 22, wherein data signals of the first data signaling type are from a first device and data signals of the second signal type are from a second device.

26. The integrated circuit of claim 25, wherein the first and second devices are located on different integrated circuits.

27. The integrated circuit of claim 21, including

a clock duty cycle detector configured to detect a duty cycle of the system clock signal and to generate a third difference signal representing a difference between the detected system clock signal duty cycle and the first predetermined duty cycle;

and

wherein the one or more correction circuits are configured to adjust the duty cycle of the receiver clock signal in accordance with the third difference signal.

28. The integrated circuit of claim 27, wherein the third difference is less than about 10% of the predetermined duty cycle.

29. The integrated circuit of claim 27, wherein the one or more correction circuits adjust the duty cycle of the receiver clock such that a difference between the duty cycle of the receiver clock and the predetermined duty cycle is less than the third difference.

30. The integrated circuit of claim 27, wherein the duty cycle correction value is applied to an amplifier circuit configured to alter the receiver clock signal duty cycle based on the duty cycle correction value.

31. The integrated circuit of claim 30, wherein the duty cycle correction value determines which transistors are turned on in a binary-weighted set of transistors.

32. The integrated circuit of claim 30, wherein the duty cycle correction value determines a voltage applied to a gate in a duty cycle correction circuit within the amplifier.

33. The integrated circuit of claim 21, including a detector configured to process the data signal using the duty cycle of the adjusted receiver clock signal.

34. The integrated circuit of claim 21, wherein the predetermined duty cycle is 50%.

35. The integrated circuit of claim 21, wherein the one or more correction circuits adjust the duty cycle of the receiver clock such that a difference between the duty cycle of the receiver clock and the first duty cycle is less than the first difference.

36. The integrated circuit of claim 21, wherein the data signal duty cycle detector generates a duty cycle correction value based on the first difference and stores the duty cycle correction value in a register.

37. The integrated circuit of claim 36, wherein the duty cycle correction value is applied to an amplifier circuit configured to alter the receiver clock signal duty cycle based on the duty cycle correction value.

38. The integrated circuit of claim 37, wherein the duty cycle correction value determines which transistors are turned on in a binary-weighted set of transistors within the amplifier circuit.

39. The integrated circuit of claim 21, wherein the first difference is less than about 10% of the predetermined duty cycle.

40. The integrated circuit of claim 21, wherein the first data signal is received from a module within the integrated circuit.

41. The integrated circuit of claim 21, wherein the first data signal is received from another integrated circuit.

42. An integrated circuit, comprising:

means for receiving a system clock signal having a duty cycle;

means for detecting a duty cycle of a data signal and for generating a first difference signal representing a difference between the detected data signal duty cycle and a predetermined duty cycle; and

means for generating a receiver clock signal based on the system clock signal and the first difference signal, including means for adjusting a duty cycle of the receiver clock signal in accordance with the first difference signal.