RFID tag design with circuitry for wafer level testing

• US 7,307,528 B2
• Filed: 12/15/2004
• Issued: 12/11/2007
• Est. Priority Date: 12/15/2004
• Status: Active Grant

• Current Assignee: Impinj, Inc.
• Original Assignee: Impinj, Inc.
• Inventors: Glidden, Robert M., Hara, Dennis Kiyoshi, Oliver, Ronald A., Kuhn, Jay A., Hyde, John D.
• Primary Examiner(s): Hofsass, Jeffery
• Assistant Examiner(s): Fan, Hongmin
• Application Number:
  US11/014,075
• Publication Number:
  US 20060125505A1
• Time in Patent Office: 1,091 Days
• Field of Search: 340/572.1, 340/572.5, 340514-515, 340/635, 340/655, 324/537, 324/754, 324/759, 324/763, 324/765, 324/755, 324/757, 324/615, 702/183
• US Class Current: 340/572.1
• CPC Class Codes: G01R 31/2822 of microwave or radiofrequency circuits of attenuation, gain, e.g. using network analyzers G01R27/28
• CPC Class Codes: G01R 31/2831 Testing of materials or semi-finished products, e.g. semiconductor wafers or substrates G01R31/318511 takes precedence; testing during manufacture H01L22/00
• CPC Class Codes: G01R 31/2884 using dedicated test connectors, test elements or test circuits on the IC under test G01R31/2855 takes precedence
• CPC Class Codes: G01R 31/3025 Wireless interface with the DUT

Abstract

Technologies suitable for on-wafer testing in the ubiquitous computing era are disclosed. Among the inventive features disclosed are: 1) clustering of wafer test probe landing area sites for parallel test sequencing; 2) on wafer test wiring that runs along the wafer'"'"'s scribe regions; 3) on-wafer test wiring that can be scribed and yet thwart the spread of contamination into the product die; 4) an RFID tag design that allows for on-wafer testing without imposing substantial semiconductor surface area penalty; 5) an RFID tag design that includes built-in self test (BIST) circuitry for the RFID tag'"'"'s non-volatile memory.

Claims

1. An apparatus, comprising:

a semiconductor chip for an RFID tag comprising a receive signal path that flows from one or more primary inputs to a controller, said receive signal path to process an electrical receive signal originating from said inputs as a consequence of said inputs having received a signal from an antenna, a second signal path flowing into said receive signal path from a die edge of said semiconductor chip, said second signal path to transport an electrical test signal that emulates said receive signal while said semiconductor chip is being tested on wafer, said receive signal path flowing through both a first input of a multiplexer circuit and said multiplexer circuit'"'"'s output, said multiplexer circuit having a second input coupled to said second signal path.

2. The apparatus of claim 1 wherein the said multiplexer circuit includes an OR gate.

3. The apparatus of claim 1 wherein said second signal path traces back to an open circuit, said open circuit caused by the scribing of said wafer.

4. The apparatus of claim 3 wherein, at the region of said open circuit, said signal path flows through said semiconductor chip'"'"'s semiconductor substrate prior to being opened as a result of scribing each individual die from the wafer.

5. The apparatus of claim 1 wherein said signal selection circuit has a channel select input, said channel select input coupled to any of:

a passive pull-up resistor,

a passive pull-down resistor,

an active pull-up device,

an active pull-down device to cause said channel select input to have a first state while said semiconductor chip is being tested on wafer and a second state while said semiconductor chip is receiving said signal from said antenna.

6. The apparatus of claim 1 wherein said semiconductor chip further comprises a rectifier coupled to at least one of said inputs, a node where a supply voltage for said semiconductor chip is to appear residing downstream from an output of said rectifier, a diode'"'"'s cathode coupled to said node, said diode'"'"'s anode coupled to wiring that provides said semiconductor chip'"'"'s supply voltage while said semiconductor chip is being tested on wafer.

7. An apparatus, comprising:

a semiconductor chip for an RFID tag comprising a receive signal path that flows from one or more primary inputs, said receive signal path to process an electrical receive signal originating from said inputs as a consequence of said inputs having received a signal from an antennae, said semiconductor chip further comprising a rectifier coupled to at least one of said inputs, a node where a supply voltage for said semiconductor chip is to appear residing downstream from an output of said rectifier, a diode'"'"'s cathode coupled to said node, said diode'"'"'s anode coupled to wiring that provides said semiconductor chip'"'"'s supply voltage while said semiconductor chip is being tested on wafer.

8. The apparatus of claim 7 wherein said semiconductor chip further comprises a multiplexer to multiplex between test signals generated while said semiconductor chip is being tested on wafer, said multiplexer having its power supply node coupled to said wiring.

9. The apparatus of claim 7 further comprising a second signal path flowing into said receive signal path from a die edge of said semiconductor chip, said second signal path to transport an electrical test signal that emulates said receive signal while said semiconductor chip is being tested on wafer, said receive signal path flowing through both a first input of a multiplexer and said multiplexer'"'"'s output, said multiplexer having a second input coupled to said second signal path, said multiplexer'"'"'s channel select input coupled to any of:

a passive pull-up resistor;

a passive pull-down resistor,

an active pull-up device;

an active pull-down device;

to cause said channel select input to have a first state while said semiconductor chip is being tested on wafer and a second state while said semiconductor chip is receiving said signal from said antenna.

10. The apparatus of claim 7 wherein said receive signal path flows to a controller.

11. The apparatus of claim 10 wherein said controller is coupled to a non-volatile memory.

12. An apparatus, comprising:

a semiconductor chip for an RFID tag comprising a receive signal path that flows from one or more primary inputs, said receive signal path to process an electrical receive signal originating from said inputs as a consequence of said inputs having received a signal from an antenna, said semiconductor chip also comprising a test signal path to transport a test signal while said semiconductor chip is being tested on wafer, said test signal path tracing from, or back to, an open circuit residing within the semiconductor substrate of said semiconductor chip, said open circuit caused by the scribing of said wafer.

13. The apparatus of claim 12 wherein said semiconductor chip further comprises a rectifier coupled to at least one of said inputs, a node where a supply voltage for said semiconductor chip is to appear residing downstream from an output of said rectifier, a diode'"'"'s cathode coupled to said node, said diode'"'"'s anode coupled to wiring that provides said semiconductor chip'"'"'s supply voltage while said semiconductor chip is being tested on wafer.

14. The apparatus of claim 13 wherein said semiconductor chip further comprises a second signal path flowing into said receive signal path from a die edge of said semiconductor chip, said second signal path to transport an electrical test signal that emulates said receive signal while said semiconductor chip is being tested on wafer.

15. The apparatus of claim 14 wherein said receive signal path flows through both a first input of a multiplexer and said multiplexer'"'"'s output, said multiplexer having a second input coupled to said second signal path.

16. The apparatus of claim 15 wherein said multiplexer'"'"'s channel select input is coupled to any of:

a passive pull-up resistor;

a passive pull-down resistor;

an active pull-up device;

a passive pull-down device

to cause said channel select input to have a first state while said semiconductor chip is being tested on wafer and a second state while said semiconductor chip is receiving said signal from said antenna.

17. The apparatus of claim 16 wherein said test signal path is said second signal path.

18. The apparatus of claim 13 wherein said semiconductor chip further comprises a multiplexer to multiplex between test signals generated while said semiconductor chip is being tested on wafer, said multiplexer having its power supply node coupled to said wiring.

19. The apparatus of claim 13 wherein said receive signal path flows to a controller.

20. The apparatus of claim 19 wherein said controller is coupled to a non-volatile memory.

21. An apparatus, comprising:

a semiconductor chip for an RFID tag comprising a receive signal path from one or more primary inputs to a controller, said receive signal path to process an electrical receive signal originating from said inputs as a consequence of said inputs having received a signal from an antenna, said semiconductor chip also comprising a response signal path that flows from said controller through an impedance controller to said inputs, said response signal path to communicate to a system that sends a wireless signal to said antenna, a third signal path flowing from said response signal path to a die edge of said semiconductor chip, said third signal path to transport a response signal while said semiconductor chip is being tested on wafer.

22. The apparatus of claim 21 wherein said third signal path flows to an open circuit residing within the semiconductor substrate of said semiconductor chip, said open circuit caused by the scribing of said wafer.

23. The apparatus of claim 21 wherein said semiconductor chip further comprises a fourth signal path flowing into said receive signal path from a die edge of said semiconductor chip, said fourth signal path to transport an electrical test signal that emulates said receive signal while said semiconductor chip is being tested on wafer.

24. The apparatus of claim 23 wherein said receive signal path flows through both a first input of a multiplexer and said multiplexer'"'"'s output, said multiplexer having a second input coupled to said fourth signal path.

25. The apparatus of claim 24 wherein said fourth signal path traces back to an open circuit, said open circuit caused by the scribing of said wafer.

26. The apparatus of claim 25 wherein, at the region of said open circuit, said signal path flows through said semiconductor chip'"'"'s semiconductor substrate.

27. The apparatus of claim 24 wherein said multiplexer'"'"'s channel select input is coupled to any of:

a passive pull-up resistor;

a passive pull-down resistor;

an active pull-up device;

an active pull-down device;

to cause said channel select input to have a first state while said semiconductor chip is being tested on wafer and a second state while said semiconductor chip is receiving said signal from said antenna.

28. The apparatus of claim 27 wherein said semiconductor chip further comprises a rectifier coupled to at least one of said inputs, a node where a supply voltage for said semiconductor chip is to appear residing downstream from an output of said rectifier, a diode'"'"'s cathode coupled to said node, said diode'"'"'s anode coupled to wiring that provides said semiconductor chip'"'"'s supply voltage while said semiconductor chip is being tested on wafer.

29. The apparatus of claim 22 wherein said semiconductor chip further comprises a rectifier coupled to at least one of said inputs, a node where a supply voltage for said semiconductor chip is to appear residing downstream from an output of said rectifier, a diode'"'"'s cathode coupled to said node, said diode'"'"'s anode coupled to wiring that provides said semiconductor chip'"'"'s supply voltage while said semiconductor chip is being tested on wafer.

30. A method, comprising:

applying a supply voltage to a semiconductor chip for an RFID tag that has not yet been diced from its wafer, said supply voltage applied to said semiconductor chip at a die edge of said semiconductor chip, a channel of a multiplexer of said semiconductor chip being enabled as a consequence of said applying; and

,

propagating a test signal through said multiplexer channel as part of testing said semiconductor chip on wafer.

31. The method of claim 30 further comprising ceasing said application of said supply voltage to said semiconductor chip after said on wafer testing of said semiconductor chip is complete.

32. The method of claim 31 further comprising dicing said semiconductor chip from said wafer.

33. The method of claim 32 further comprising receiving a wireless signal at an antenna coupled to, said semiconductor chip generating a second supply voltage in response, another channel of said multiplexer being enabled as a consequence of said generating.

34. The method of claim 33 wherein:

data carried by said wireless signal flows through said another channel; and

,

said test signal includes test data intended to emulate wirelessly received data.

35. The method of claim 34 wherein, prior to said propagating said test signal through said multiplexer, said test signal was propagated through a scribe region of said wafer.

36. The method of claim 30 wherein said test signal includes test data intended to emulate wirelessly received data.

37. The method of claim 36 wherein said semiconductor chip comprises a controller coupled to non-volatile memory, said test data being write data to be written into said non-volatile memory by said controller.

38. The method of claim 37 wherein said test signal includes a command for said controller that causes said controller to write said test data into said non-volatile memory.

39. The method of claim 38 further comprising sending a second command to said controller through said multiplexer channel as part of testing said semiconductor chip on wafer, said second command to cause said controller to read data from said non-volatile memory.

40. The method of claim 39 further comprising sending said data read from said non-volatile memory off said semiconductor chip to a wafer test probe.

41. The method of claim 30 further comprising after said applying and prior to said propagating:

specifically addressing said semiconductor chip from a wafer test probe, said test signal received by said semiconductor chip as well as other semiconductor chips on said wafer, said addressing to ensure that said test signal is applied at said semiconductor chip and not at said other semiconductor chips.

42. The method of claim 41 wherein said wafer test probe also sends said test signal.

43. The method of claim 41 wherein said addressing further comprises sending an identifier to said semiconductor chip as well as said other semiconductor chips, said identifier matching said semiconductor chip'"'"'s identifier and not any of said other semiconductor chips'"'"' identifiers, each identifier being uniquely coded into its respective semiconductor chip.

44. The method of claim 30 wherein said semiconductor chip comprises a controller coupled to non-volatile memory, said method comprising sending write data to said semiconductor chip as part of testing said semiconductor chip on wafer, said write data to be written into said non-volatile memory by said controller, said write data containing information that emulates said semiconductor chip'"'"'s identification.

45. The method of claim 30 wherein a multiplexer designed into said semiconductor chip is powered from said applying but not from said semiconductor chip'"'"'s generation of its supply voltage from its reception of a signal received from an antenna.