Nonvolatile semiconductor static random access memory device
First Claim
1. A nonvolatile semiconductor memory device including a plurality of data registers,wherein each of the plurality of data registers comprises:
- a storage node;
a pull-up driving unit adapted and configured to pull up the storage node and having a latch structure where its control terminal is cross-coupled with the storage node;
a pull-down driving unit adapted and configured to pull down the storage node and having a latch structure where its control terminal is cross-coupled with the storage node;
a data input/output unit adapted and configured to selectively input and output data between a bit line and the storage node depending on a voltage applied to a word line; and
a data storing unit adapted and configured to store data of the storage node in a ferroelectric layer depending on a voltage applied to a top word line and a bottom word line or to output data that corresponds to resistance change of a float channel layer according to a polarization state of charges stored in the ferroelectric layer to the storage node and read the outputted data.
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Abstract
A nonvolatile semiconductor memory device obtained by combining a nonvolatile memory device with a SRAM is provided to improve operating speed and reliability. The nonvolatile semiconductor memory device includes a plurality of data registers. Preferably, each of the plurality of data registers includes a pull-up driving unit adapted and configured to pull up a storage node, a pull-down driving unit adapted and configured to pull down the storage node, a data input/output unit adapted and configured to selectively input and output data between a bit line and the storage node depending on a voltage applied to a word line, and a data storing unit adapted and configured to store data of the storage node depending on a voltage applied to a top word line and a bottom word line or to output the stored data to the storage node.
34 Citations
17 Claims
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1. A nonvolatile semiconductor memory device including a plurality of data registers,
wherein each of the plurality of data registers comprises: -
a storage node; a pull-up driving unit adapted and configured to pull up the storage node and having a latch structure where its control terminal is cross-coupled with the storage node; a pull-down driving unit adapted and configured to pull down the storage node and having a latch structure where its control terminal is cross-coupled with the storage node; a data input/output unit adapted and configured to selectively input and output data between a bit line and the storage node depending on a voltage applied to a word line; and a data storing unit adapted and configured to store data of the storage node in a ferroelectric layer depending on a voltage applied to a top word line and a bottom word line or to output data that corresponds to resistance change of a float channel layer according to a polarization state of charges stored in the ferroelectric layer to the storage node and read the outputted data. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17)
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Specification