Concurrent programming of non-volatile memory

• US 7,307,884 B2
• Filed: 06/15/2004
• Issued: 12/11/2007
• Est. Priority Date: 06/15/2004
• Status: Active Grant

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: SanDisk Corporation (Western Digital Corporation)
• Inventors: Guterman, Daniel C.
• Primary Examiner(s): Phung; Anh
• Assistant Examiner(s): NGUYEN, DANG T
• Application Number:
  US10/868,147
• Publication Number:
  US 20050276108A1
• Time in Patent Office: 1,274 Days
• Field of Search: 365/185.17, 365/185.18, 365/185.28, 365/185.33, 365/185.23, 365/185.24, 365/189.04, 365/185.05, 365/185.11
• US Class Current: 365/185.18
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/10 Programming or data input circuits

Abstract

One embodiment of the present invention includes applying a first value to a bit line, boosting word lines associated with the bit line and a common selection line to create a first condition based on the first value, and cutting off a boundary non-volatile storage element associated with the common selection line to maintain the first condition for a particular non-volatile storage element associated with the bit line and common selection line. A second value is applied to the bit line and at least a subset of the word lines are boosted to create a second condition for a different non-volatile storage element associated with the bit line and common selection line. The second condition is based on the second value. The first condition and the second condition overlap in time. Both non-volatile storage elements are programmed concurrently, based on their associated conditions.

Claims

1. A method for programming non-volatile storage, comprising:

writing data to a first non-volatile storage element on a first NAND string; and

writing data to a second non-volatile storage element on said first NAND string, said writing data to said first non-volatile storage element overlaps in time with said writing data to said second non-volatile storage element.

2. A method according to claim 1, wherein:

said step of writing data to a first non-volatile storage element includes applying multiple program pulses, including a first program pulse, to a control gate for said first non-volatile storage element; and

said step of writing data to a second non-volatile storage element includes applying multiple program pulses to a control gate for said second non-volatile storage element, including applying a second program pulse to said control gate for said second non-volatile storage element while applying said first program pulse to said control gate for said first non-volatile storage element.

3. A method according to claim 1, wherein:

said step of writing data to a first non-volatile storage element includes establishing a first write condition for said first non-volatile storage element; and

said step of writing data to a second non-volatile storage element includes establishing a second write condition for said second non-volatile storage element, said second write condition is separate from said first write condition.

4. A method according to claim 3, wherein:

said first write condition includes a channel voltage at or near 0 volts; and

said second write condition includes a channel voltage at or near an inhibit level.

5. A method according to claim 3, wherein:

said first write condition includes a channel voltage at or near 0 volts; and

said second write condition includes a channel voltage at or near a level that retards but does not inhibit programming.

6. A method according to claim 1, further comprising:

writing data to a third non-volatile storage element on a second NAND string while writing data to said first non-volatile storage element; and

writing data to a fourth non-volatile storage element on said second NAND string while writing data to said second non-volatile storage element, said writing data to said third non-volatile storage element overlaps in time with said writing data to said fourth non-volatile storage element.

7. A method according to claim 1, further comprising:

writing data to a third non-volatile storage element on said first NAND string, said writing data to said third non-volatile storage element overlaps in time with said writing data to said first non-volatile storage element.

8. A method according to claim 7, further comprising:

writing data to a fourth non-volatile storage element on said first NAND string, said writing data to said fourth non-volatile storage element overlaps in time with said writing data to said first non-volatile storage element.

9. A method according to claim 1, wherein:

said first NAND string includes a first group of non-volatile storage elements and a second group of non-volatile storage elements;

said first group includes said first non-volatile storage element;

said second group includes said second non-volatile storage element;

said first NAND string includes a boundary storage element which serves at a boundary between said first group and said second group for at least a period of time; and

said first NAND string includes a select gate.

10. A method according to claim 9, wherein said steps of writing data to a first non-volatile storage element and writing data to a second non-volatile storage element comprise:

applying a first value to a bit line associated with said first NAND string;

boosting word lines associated with said first NAND string to create a first condition for said first group based on said first value;

cutting off said boundary storage element to maintain said first condition for said first group;

applying a second value to said bit line; and

boosting at least a subset of said word lines associated with said first NAND string to create a second condition for said second group based on said second value, said first condition and said second condition overlap in time.

11. A method according to claim 10, wherein:

said step of writing data to a first non-volatile storage element includes applying a first program pulse to a control gate for said first non-volatile storage element; and

said step of writing data to a second non-volatile storage element includes applying a second program pulse to a control gate for said second non-volatile storage element while applying said first program pulse to said control gate for said first non-volatile storage element.

12. A method according to claim 1, wherein:

said first non-volatile storage element and said second non-volatile storage element are multi-state NAND flash memory transistors.

13. A method according to claim 1, wherein:

said first NAND string is on a removable memory card.

14. A non-volatile storage system, comprising:

a group of non-volatile storage elements associated with a common bit line and a common selection line, said group includes a first non-volatile storage element and a second non-volatile storage element; and

a control circuit, said control circuit writes data to said first non-volatile storage element, said control circuit writes data to said second non-volatile storage element while writing data to said first non-volatile storage element, said control circuit applies a first value to said common bit line, boosts word lines associated with said group to create a first condition for said first non-volatile storage element based on said first value, cuts off a boundary storage element associated with said group to maintain said first condition for said first non-volatile storage element, applies a second value to said common line, and boosts at least a subset of said word lines associated with said group to create a second condition for a second non-volatile storage element based on said second value, wherein said first condition and said second condition overlap in time.

15. A non-volatile storage system according to claim 14, wherein:

said group includes a third non-volatile storage element and a fourth non-volatile storage element;

said control circuit writes data to said third non-volatile storage element while writing data to said first non-volatile storage element; and

said control circuit writes data to said fourth non-volatile storage element while writing data to said first non-volatile storage element.

16. A non-volatile storage system according to claim 14, wherein

said control circuit writes data to said first non-volatile storage element by applying multiple program pulses, including a first program pulse, to a control gate for said first non-volatile storage element;

and

said control circuit writes data to said second non-volatile storage element by applying multiple program pulses to a control gate for said second non-volatile storage element, including applying a second program pulse to said control gate for said second non-volatile storage element while applying said first program pulse to said control gate for said first non-volatile storage element.

17. A non-volatile storage system according to claim 16, wherein:

said group of non-volatile storage elements include NAND flash memory devices on a NAND string; and

said common selection line is a drain side select gate control line for said NAND string.

18. A non-volatile storage system according to claim 14, wherein:

said control circuit includes a controller, a state machine, decoders, and sense amplifiers.

30. A non-volatile storage system according to claim 14, wherein:

said group of non-volatile storage elements have channels in a common well.

31. A non-volatile storage system according to claim 14, wherein:

said group of non-volatile storage elements have channels in a common p-well.

19. A non-volatile storage system, comprising:

a NAND string comprising a set of non-volatile storage elements; and

a control circuit in communication with said NAND string, said control circuit writes data to a first non-volatile storage element on said NAND string and writes data to a second non-volatile storage element on said NAND string, said writing data to said first non-volatile storage element overlaps in time with said writing data to said second non-volatile storage element.

20. A non-volatile storage system according to claim 19, wherein:

said control circuit establishes a first write condition on said NAND string for said first non-volatile storage element and establishes a second write condition on said NAND string for said second non-volatile storage element, said second write condition is separate from said first write condition.

21. A non-volatile storage system according to claim 19, wherein:

said NAND string includes a third non-volatile storage element and a fourth non-volatile storage element;

said control circuit writes data to said third non-volatile storage element while writing data to said first non-volatile storage element; and

said control circuit writes data to said fourth non-volatile storage element while writing data to said first non-volatile storage element.

22. A non-volatile storage system according to claim 19, wherein:

said control circuit applies a first value to a bit line for said NAND string, boosts word lines associated with said NAND string to create a first condition for said first non-volatile storage element based on said first value, cuts off a boundary storage element associated with said NAND string to maintain said first condition for said first non-volatile storage element, applies a second value to said bit line for said NAND string, and boosts at least a subset of said word lines to create a second condition for a second non-volatile storage element based on said second value, said first condition and said second condition overlap in time.

32. A non-volatile storage system according to claim 19, wherein:

said control circuit writes data to said first non-volatile storage element by applying a plurality of program pulses to a control gate for said first non-volatile storage element; and

said control circuit writes data to said second non-volatile storage element by applying a plurality of program pulses to a control gate for said second non-volatile storage element.

23. A non-volatile storage system, comprising:

a plurality of NAND strings, each of said NAND strings includes non-volatile storage elements; and

a control circuit in communication with said NAND strings, said control circuit causes concurrent writing of data to multiple non-volatile storage elements within each of said NAND strings.

24. A non-volatile storage system according to claim 23, wherein:

said plurality of NAND strings includes a first NAND string and a second NAND string;

said first NAND string includes a first non-volatile storage element, a second non-volatile storage element and a third non-volatile storage element;

said second NAND string includes a fourth non-volatile storage element, a fifth non-volatile storage element and a sixth non-volatile storage element;

said third non-volatile storage element and said sixth non-volatile storage element are boundary storage elements;

said control circuit writes data to said first non-volatile storage element on said first NAND string, writes data to said second non-volatile storage element on said first NAND string, writes data to said fourth non-volatile storage element on said second NAND string, and writes data to said fifth non-volatile storage element on said second NAND string;

said writing data to said first non-volatile storage element overlaps in time with said writing data to said second non-volatile storage element; and

said writing data to said fourth non-volatile storage element overlaps in time with said writing data to said fifth non-volatile storage element.

25. A non-volatile storage system according to claim 23, wherein:

said control circuit establishes multiple write conditions on each NAND string.

26. A non-volatile storage system, comprising:

a set of non-volatile storage elements organized into groups, each group includes multiple non-volatile storage elements in series, said groups include a first group, said first group includes a first non-volatile storage element and a second non-volatile storage element having channels associated with a first selection line, said first non-volatile storage element is in series with said second non-volatile storage element; and

a control circuit in communication with said groups, said control circuit writes data to said first non-volatile storage element and writes data to said second non-volatile storage element, said writing of data to said first non-volatile storage element overlaps in time with said writing of data to said second non-volatile storage element.

27. A non-volatile storage system according to claim 26, wherein:

said control circuit establishes a first write condition in said first group for said first non-volatile storage element and establishes a second write condition in said first group for said second non-volatile storage element, said second write condition is separate from said first write condition.

28. A non-volatile storage system according to claim 27, wherein:

said control circuit applies a first value to said first selection line, boosts control lines associated with said first group to create a first condition for said first non-volatile storage element based on said first value, cuts off a boundary storage element in said first group to maintain said first condition for said first non-volatile storage element, applies a second value to said first selection line, and boosts at least a subset of said control lines to create a second condition for said second non-volatile storage element based on said second value, said first condition and said second condition overlap in time.

29. A non-volatile storage system according to claim 26, wherein:

said first non-volatile storage element and said second non-volatile storage element have channels in a common well.