Technique for receiving differential multi-PAM signals
First Claim
1. A differential multiple pulse amplitude modulated (multi-PAM) extractor circuit comprising:
- an upper least significant bit (LSB) sampler circuit configured to receive a differential multi-PAM input signal and a first differential reference signal, and to generate a first differential sampled output signal;
a lower LSB sampler circuit configured to receive the differential multi-PAM input signal and a second differential reference signal, and to generate a second differential sampled output signal; and
a combiner circuit configured to receive the first differential sampled output signal and the second differential sampled output signal, and to generate a differential LSB output signal indicating an LSB value of the differential multi-PAM input signal.
1 Assignment
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Accused Products
Abstract
A technique for receiving differential multi-PAM signals is disclosed. In one particular exemplary embodiment, the technique may be realized as a differential multi-PAM extractor circuit. In this particular exemplary embodiment, the differential multi-PAM extractor circuit comprises an upper LSB sampler circuit configured to receive a differential multi-PAM input signal and a first differential reference signal, and to generate a first differential sampled output signal. The differential multi-PAM extractor circuit also comprises a lower LSB sampler circuit configured to receive the differential multi-PAM input signal and a second differential reference signal, and to generate a second differential sampled output signal. The differential multi-PAM extractor circuit further comprises a combiner circuit configured to receive the first differential sampled output signal and the second differential sampled output signal, and to generate a differential LSB output signal indicating an LSB value of the differential multi-PAM input signal.
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Citations
52 Claims
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1. A differential multiple pulse amplitude modulated (multi-PAM) extractor circuit comprising:
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an upper least significant bit (LSB) sampler circuit configured to receive a differential multi-PAM input signal and a first differential reference signal, and to generate a first differential sampled output signal; a lower LSB sampler circuit configured to receive the differential multi-PAM input signal and a second differential reference signal, and to generate a second differential sampled output signal; and a combiner circuit configured to receive the first differential sampled output signal and the second differential sampled output signal, and to generate a differential LSB output signal indicating an LSB value of the differential multi-PAM input signal. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16)
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17. A differential multiple pulse amplitude modulated (multi-PAM) extractor circuit comprising:
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a pair of input transistors configured to receive a differential multi-PAM input signal; a pair of equalization transistors, coupled to the pair of input transistors, and configured to receive a differential equalization signal; a linear load coupled to the pair of input transistors and the pair of equalization transistors; and a pair of current sources coupled to the pair of input transistors and the pair of equalization transistors, respectively; wherein the differential equalization signal has a common-mode similar to the differential multi-PAM input signal.
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18. A differential multiple pulse amplitude modulated (multi-PAM) extractor circuit comprising:
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a pair of input transistors configured to receive a differential multi-PAM input signal; a pair of equalization transistors, coupled to the pair of input transistors, and configured to receive a differential equalization signal; a nonlinear load coupled to the pair of input transistors and the pair of equalization transistors; and a pair of switches coupled to the pair of input transistors and the pair of equalization transistors, respectively; wherein the differential equalization signal has a common-mode similar to the differential multi-PAM input signal. - View Dependent Claims (19, 20)
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21. A differential multiple pulse amplitude modulated (multi-PAM) extractor circuit comprising:
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first and second pairs of input transistors configured to receive a differential multi-PAM input signal; first and second pairs of adjustable resistive elements, coupled to the first and second pairs of input transistors, respectively, and configured to receive a differential control signal; a load coupled to the first and second pairs of input transistors; and a pair of current sources coupled to the first and second pairs of adjustable resistive elements, respectively; wherein the differential control signal is applied to the first and second pairs of adjustable resistance elements so as to adjust their resistance value. - View Dependent Claims (22)
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23. A differential multiple pulse amplitude modulated (multi-PAM) extractor circuit comprising:
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first and second pairs of adjustable voltage sources connected in series with signal paths for a differential multi-PAM input signal, the first and second pairs of adjustable voltage sources configured to receive a differential control signal; first and second pairs of input transistors, coupled to the first and second pairs of adjustable voltage sources, respectively, and configured to receive voltage adjusted differential multi-PAM input signals from the first and second pairs of adjustable voltage sources, respectively; a load coupled to the first and second pairs of input transistors; and a pair of current sources coupled to the first and second pairs of input transistors, respectively. - View Dependent Claims (24, 25, 26, 27)
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28. A differential multiple pulse amplitude modulated (multi-PAM) extractor circuit comprising:
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a differential amplifier circuit configured to receive a differential multi-PAM input signal and to generate an amplified differential multi-PAM signal; a differential automatic gain control circuit, coupled to the differential amplifier circuit, and configured to control gain in the differential amplifier circuit; a first differential sampler circuit, coupled to the differential amplifier circuit and the differential automatic gain control circuit, and configured to sample the amplified differential multi-PAM signal and to generate a first output signal indicating a most significant bit value of the differential multi-PAM input signal; and a second differential sampler circuit, coupled to the differential amplifier circuit and the differential automatic gain control circuit, and configured to sample the amplified differential multi-PAM signal and to generate a second output signal indicating a least significant bit value of the differential multi-PAM input signal. - View Dependent Claims (29)
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30. A differential multiple pulse amplitude modulated (multi-PAM) extractor circuit comprising:
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a first differential amplifier circuit configured to receive a differential multi-PAM input signal and to generate a first amplified differential multi-PAM signal; a second differential amplifier circuit configured to receive the differential multi-PAM input signal and to generate a second amplified differential multi-PAM signal; a first differential automatic gain control circuit, coupled to the first differential amplifier circuit, and configured to control gain in the first differential amplifier circuit; a second differential automatic gain control circuit, coupled to the second differential amplifier circuit, and configured to control gain in the second differential amplifier circuit; a first differential sampler circuit, coupled to the first differential amplifier circuit and the first differential automatic gain control circuit, and configured to sample the first amplified differential multi-PAM signal and to generate a first output signal indicating a most significant bit value of the differential multi-PAM input signal; and a second differential sampler circuit, coupled to the second differential amplifier circuit and the second differential automatic gain control circuit, and configured to sample the second amplified differential multi-PAM signal and to generate a second output signal indicating a least significant bit value of the differential multi-PAM input signal. - View Dependent Claims (31)
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32. A differential multiple pulse amplitude modulated (multi-PAM) extractor circuit comprising:
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a first differential amplifier circuit configured to receive a differential multi-PAM input signal and to generate a first amplified differential multi-PAM signal; a second differential amplifier circuit configured to receive the differential multi-PAM input signal and to generate a second amplified differential multi-PAM signal; a differential automatic gain control circuit, coupled to the first differential amplifier circuit and the second differential amplifier circuit, and configured to control gain in the first differential amplifier circuit and the second differential amplifier circuit based at least in part upon the first amplified differential multi-PAM signal; a first differential sampler circuit, coupled to the first differential amplifier circuit and the differential automatic gain control circuit, and configured to sample the first amplified differential multi-PAM signal and to generate a first output signal indicating a most significant bit value of the differential multi-PAM input signal; and a second differential sampler circuit, coupled to the second differential amplifier circuit, and configured to sample the second amplified differential multi-PAM signal and to generate a second output signal indicating a least significant bit value of the differential multi-PAM input signal. - View Dependent Claims (33)
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34. A differential multiple pulse amplitude modulated (multi-PAM) extractor circuit comprising:
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a plurality of differential amplifier circuits configured to receive a differential multi-PAM input signal and to generate a plurality of amplified differential multi-PAM signals; a plurality of adjustable offset voltage sources, coupled to the plurality of differential amplifier circuits, respectively, and configured to provide a plurality of offset voltage signals to the plurality of differential amplifier circuits, respectively; and a plurality of differential multiple-sampler circuits, coupled to the plurality of differential amplifier circuits, respectively, and configured to multiple-sample the plurality of amplified differential multi-PAM signals, respectively, to generate a plurality of multiple-sampled multi-PAM signals, respectively, and to determine a most significant bit value and a least significant bit value of the differential multi-PAM input signal. - View Dependent Claims (35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52)
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Specification