System and method for selecting optimal data transition types for clock and data recovery

• US 7,308,048 B2
• Filed: 03/09/2004
• Issued: 12/11/2007
• Est. Priority Date: 03/09/2004
• Status: Active Grant

• Current Assignee: Rambus Inc.
• Original Assignee: Rambus Inc.
• Inventors: Wei, Jason
• Primary Examiner(s): Kim, Kevin
• Application Number:
  US10/797,443
• Publication Number:
  US 20050201491A1
• Time in Patent Office: 1,372 Days
• Field of Search: 375/376, 375/371, 375/360, 375/293, 375/326
• US Class Current: 375/326
• CPC Class Codes: H04L 27/01 Equalisers baseband equalizers at the transmitter end H04L25/03343; in analogue transmission systems H04B3/04, H04B7/005
• CPC Class Codes: H04L 27/02 Amplitude-modulated carrier systems, e.g. using on-off keying; Single sideband or vestigial sideband modulation H04L27/32 takes precedence
• CPC Class Codes: H04L 7/0337 Selecting between two or more discretely delayed clocks or selecting between two or more discretely delayed received code signals

Abstract

A clock recovery circuit samples an incoming data stream that includes sequences of signal transitions. A transition detector categorizes the received signal transitions into various types, such as those associated with 2PAM and 4PAM signaling schemes. Select logic control circuitry analyzes the signal-transition types to determine which of the transition types is best suited for clock recovery. This determination relies upon a number of factors, including for example whether the received signal is a 4PAM signal or a 2PAM signal, the existence of a pattern within the received data, or the relative abundance or scarcity of certain types of transitions.

Claims

1. A clock recovery circuit comprising:

a. transition detector that receives a plurality of data transitions of various data-transition types, the transition detector including a plurality of data-transition output terminals, each data-transition output terminal producing a data-transition signal in response to a respective one of the data-transition types;

b. transition select logic having a plurality of select-logic input nodes, a select-logic output node, and select-logic control terminals, each select-logic input node coupled to a respective one of the data-transition output terminals, wherein the transition select logic conveys at least one of the data-transition signals from a respective one of the select-logic input nodes to the select-logic output node in response to select-logic control signals to the select-logic control terminals; and

c. a select-logic control circuit having control-circuit output terminals coupled to the select logic control terminals;

wherein the select-logic control circuit issues transition select signals to the transition select logic via the select logic control terminals.

2. The clock recovery circuit of claim 1, wherein the select-logic control circuit issues the transition select signals in response to at least one of the data-transition signals.

3. The clock recovery circuit of claim 2, wherein the select-logic control circuit includes control-circuit input terminals coupled to respective ones of the data-transition output terminals.

4. The clock recovery circuit of claim 1, wherein the data-transition types include 2PAM and 4PAM data transitions.

5. The clock recovery circuit of claim 1, wherein the select-logic control circuit issues select-logic control signals that cause the transition select logic to select data transitions of a first type in the absence of a minimum number of data transitions of a second type.

6. The clock recovery circuit of claim 5, wherein the data transitions of the first type are 2PAM data transitions and the data transitions of the second type are 4PAM data transitions.

7. The clock recovery circuit of claim 1, further comprising a data sampler that samples a received data stream to provide a sampled data stream, the sampled data stream including the plurality of data transitions.

8. The clock recovery circuit of claim 7, further comprising a phase mixer coupled between the transition-select logic and the sampler, wherein the phase mixer provides a clock signal to the sampler.

9. The clock recovery circuit of claim 1, the select-logic control circuit including a transition analyzer that receives the data-transition signals.

10. The clock recovery circuit of claim 9, wherein the transition analyzer counts the data-transition signals associated with different ones of the data-transition types.

11. The clock recovery circuit of claim 9, wherein the transition analyzer examines patterns associated with at least one of the data-transition types.

12. The clock recovery circuit of claim 9, wherein the transition analyzer issues transition vectors based upon the data-transition signals.

13. The clock recover circuit of claim 12, the select-logic control circuit including a mode generator coupled between the transition analyzer and the transition select logic, wherein the mode generator issues transition select signals in response to the data-transition vectors.

14. A clock recovery method comprising:

a. sampling a data stream using a receive clock to generate sampled data;

b. monitoring the sampled data for data transitions of a plurality of possible data-transition types;

c. automatically selecting a subset of the data transitions based upon the monitoring;

d. adjusting the receive clock relative to the sampled data using the subset of the data transitions; and

e. wherein automatically selecting the subset of the data transitions includes determining whether the data stream is a multi-level signal.

15. The clock recovery method of claim 14, wherein the data stream is a multi-level signal.

16. The clock recovery method of claim 15, wherein the data stream is a multi-PAM signal.

17. The clock recovery method of claim 14, wherein automatically selecting the subset of the data transitions includes determining whether the data stream is a multi-PAM signal.

18. A clock recovery method comprising:

a. sampling a data stream using a receive clock to generate sampled data;

b. monitoring the sampled data for data, transitions of a plurality of possible data-transition types;

c. automatically selecting a subset, of the data transitions based upon the monitoring; and

d. adjusting the receive clock relative to the sampled data using the subset of the data transitions;

e. wherein automatically selecting a subset of the data transitions comprises separating the data transitions into at least two of the data-transition types.

19. The clock recovery method of claim 18, wherein automatically selecting a subset of the data transitions comprises matching a sequence of at least one of the data-transition types to a pattern.

20. The clock recovery method of claim 18, wherein automatically selecting a subset of the data transitions comprises counting data transitions of at least one of the data-transition types.

21. The clock recovery method of claim 18, wherein a majority of the data transitions are of a first of the data-transition types, the method further comprising adjusting the phase of the receive clock in response to the first data-transition type.

22. A clock recovery dircuit comprising:

a. a transition detector that receives a plurality of data transitions of various data-transition types, the transition detector including a plurality of data-transition output terminals, each data-transition output terminal producing a data-transition signal in response to a respective one of the data-transition types;

b. transition select logic having a plurality of select-logic input nodes, a select-logic output node, and select-logic control terminals, each select-logic input node coupled to a respective one of the data-transition output terminals, wherein the transition select logic conveys at least one of the data-transition signals from a respective one of the select-logic input nodes to the select-logic output node in response to select-logic control signals to the select-logic control terminals; and

c. control means connected to the select-logic control terminals, wherein the control means issues transition select signals to the transition select logic in response to the data transitions.

23. The clock recovery circuit of claim 22, wherein the transition select signals select a predominant one of the data-transition types.

24. A clock recovery circuit comprising:

a. a transition detector that receives a plurality of data transitions of various data-trahsition types;

b. transition select logic that receives the data transitions and that conveys a feedback signal in response to at least one of the data-transition types; and

c. a select-logic control circuit that controls the transition select logic to select the at least one of the data-transition types based on the received data transitions.

25. The clock recovery circuit of claim 24, wherein the select-logic control circuit controls the transition select logic to select a predominate data-transition type.

26. The clock recovery circuit of claim 24, wherein the select-logic control circuit repeatedly controls the transition select logic to convey the feedback signal in response to different data-transition types.

27. A clock recovery circuit comprising:

a. a transition detector that receives a plurality of data transitions of various data-transition types and produces unique data-transition signals in response to respective ones of the data-transition types; and

b. select logic that selects ones of the data-transition signals based upon the received data-transition types.

28. The clock recovery circuit of claim 27, wherein the select logic includes a select-logic control circuit and transition select logic.

29. The clock recovery circuit of claim 27, wherein the select-logic control circuit issues transition select signals to the transition select logic in response to at least one of the data-transition signals.

30. The clock recovery circuit of claim 29, wherein the transition detector includes a plurality of output nodes, wherein each output node conveys one type of the data-transition signals.

31. The clock recovery circuit of claim 29, wherein the select-logic control circuit includes control-circuitinput terminals coupled to respective ones of the data-transition output terminals.

32. The clock recovery circuit of claim 27, wherein the data-transition types include 2PAM and 4PAM data transitions.

33. The clock recovery circuit of claim 27, wherein the select-logic control circuit issues select-logic control signals that cause the transition select logic to select data transitions ofa first type in the absence of a minimum number of data transitions of a second type.

34. The clock recovery circuit of claim 33, wherein the data transitions of the first type are 2PAM data transitions and the data transitions of the second type are 4PAM data transitions.

35. The clock recovery circuit of claim 27, further comprising a data sampler that samples a received data stream to provide a sampled data stream, the sampled data stream including the plurality of data transitions.

36. The clock recovery circuit of claim 35, further comprising a phase mixer coupled between the select logic and the sampler, wherein the phase detector provides a clock signal to the sampler.

37. The clock recovery circuit of claim 27, the select logic including a transition analyzer that receives the data-transition signals.

38. The clock recovery circuit of claim 37, wherein the transition analyzer counts the data-transition signals associated with different ones of the data-transition types.

39. The clock recovery circuit of claim 37, wherein the transition analyzer examines patterns associated with at least one of the data-transition types.

40. The clock recovery circuit of claim 37, wherein the transition analyzer issues transition vectors based upon the data-transition signals.

41. The clock recovery circuit of claim 39, wherein theselect logic includes a mode generator coupled between the transition analyzer and the transition select logic, and wherein the mode generator issues transition select signals in response to the data-transition vectors.