Transparent multi-mode PAM interface

• US 7,308,058 B2
• Filed: 03/19/2004
• Issued: 12/11/2007
• Est. Priority Date: 10/27/2003
• Status: Active Grant

• Current Assignee: Rambus Inc.
• Original Assignee: Rambus Inc.
• Inventors: Zerbe, Jared L., Werner, Carl W., Stonecypher, William F., Chen, Fred F.
• Primary Examiner(s): Ghayour, Mohammed
• Assistant Examiner(s): King, Sonia J
• Application Number:
  US10/805,413
• Publication Number:
  US 20050089126A1
• Time in Patent Office: 1,362 Days
• Field of Search: 375/353, 375/286, 375/224, 375/219, 375/259
• US Class Current: 375/353
• CPC Class Codes: H04L 1/0003 by switching between different modulation schemes
• CPC Class Codes: H04L 2025/03585 Modifying the length
• CPC Class Codes: H04L 25/028 Arrangements specific to the transmitter end
• CPC Class Codes: H04L 25/0292 Arrangements specific to the receiver end
• CPC Class Codes: H04L 25/4917 using multilevel codes
• CPC Class Codes: H04L 27/08 Amplitude regulation arrangements
• CPC Class Codes: H04L 5/1438 Negotiation of transmission parameters prior to communication modified according to link quality H04L1/0001

Abstract

Provided are a method and apparatus for high-speed, multi-mode PAM symbol transmission. A multi-mode PAM output driver drives one or more symbols, the number of levels used in the PAM modulation of the one or more symbols depending on the state of a PAM mode signal. Additionally, the one or more symbols are driven at a symbol rate, the symbol rate selected in accordance with the PAM mode signal so that a data rate of the driven symbols is constant with respect to changes in the state of the PAM mode signal. Further provided are methods for determining the optimal number of PAM levels for symbol transmission and reception in a given physical environment.

Claims

1. A multi-mode PAM output driver for driving a sequence of symbols, the output driver comprising:

an input interface configured to receive data to be output as the sequence of symbols;

an interface configured to receive a PAM mode signal specifying a PAM mode;

multiplexer circuitry configured to output the received data in an order determined by the PAM mode signal;

a clock circuit configured to generate an output clock having a clock rate determined by the PAM mode signal;

a driver circuit coupled to the clock circuit and to an output of the multiplexer circuit, the driver circuit configured to drive the sequence of symbols, the symbols driven in the order output by multiplexer circuit.

2. The multi-mode PAM output driver of claim 1,

wherein the sequence of symbols are N-PAM symbols when the PAM mode is a first PAM mode;

wherein the sequence of symbols are M-PAM symbols when the PAM mode is a second PAM mode; and

wherein N is not equal to M.

3. The multi-mode PAM output driver of claim 2, wherein N and M are each selected from the group consisting of 2, 4, 8, 16, and 32.

4. The multi-mode PAM output driver of claim 2, wherein N and M are each selected from the group consisting of 2 and 4.

5. The multi-mode PAM output driver of claim 1, wherein the multiplexer circuitry and the clock circuit are configured such that a total output data rate of the multi-mode PAM output driver is the same for a first PAM mode and a second PAM mode.

6. The multi-mode PAM output driver of claim 2, wherein the multiplexer circuitry and clock circuit are configured such that a total output data rate of the multi-mode PAM output driver is the same for the first PAM mode and the second PAM mode.

7. The multi-mode PAM output driver of claim 2,

wherein the clock rate in the first PAM mode is twice the clock rate in the second PAM mode, and

wherein each symbol in the sequence of symbols output in the second PAM mode carries twice as much information as each symbol in the sequence of symbols output in the first PAM mode.

8. The multi-mode PAM output driver of claim 1, further comprising control circuitry configured to determine the PAM mode.

9. The multi-mode PAM output driver of claim 1,

further comprising an interface configured to receive a word length mode signal specifying a word length mode;

wherein the multiplexer circuitry is further configured to order the received data in accordance with the word length mode; and

wherein the clock circuit is configured to generate the output clock at a clock rate determined, at least in part, by the PAM mode signal and the word length mode.

10. The multi-mode PAM output driver of claim 1,

further comprising an interface configured to receive a byte length mode signal specifying a byte length mode;

wherein the multiplexer circuitry is configured to order the received data in an order determined, at least in part, by the PAM mode signal and the byte length mode signal.

11. The multi-mode PAM output driver of claim 10,

wherein the clock circuit is configured to generate the output clock at a clock rate determined, at least in part, by the PAM mode signal and the byte length mode signal.

12. The multi-mode PAM output driver of claim 1, wherein the driver circuit comprises a first pipeline and a second pipeline, the first and second pipeline configured to store the ordered data received from the multiplexer circuit.

13. The multi-mode PAM output driver of claim 12, wherein the driver circuit is configured to disable the first pipeline when the PAM mode is a first PAM mode.

14. A multi-mode PAM receiver for receiving a sequence of symbols, the receiver comprising:

an interface configured to receive a PAM mode signal specifying a PAM mode;

a receive clock signal;

a receiver circuit configured to receive the sequence of symbols at a clock rate of the receive clock signal and to generate a corresponding data stream;

multiplexer circuitry configured to order data from the data stream in accordance with the PAM mode signal so as to produce a formatted data stream; and

an output interface coupled to an output of the multiplexer circuitry, the output interface configured to output data words from the formatted data stream at a rate determined, at least in part, by the PAM mode.

15. The multi-mode PAM receiver of claim 14,

wherein the sequence of symbols are N-PAM symbols when the PAM mode is a first PAM mode;

wherein the sequence of symbols are M-PAM symbols when the PAM mode is a second PAM mode; and

wherein N is not equal to M.

16. The multi-mode PAM receiver of claim 15, wherein N and M are selected from the group consisting of 2, 4, 8, 16, and 32.

17. The multi-mode PAM receiver of claim 15, wherein N and M are selected from the group consisting of 2 and 4.

18. The multi-mode PAM receiver of claim 14, wherein the receiver circuit is configured to operate so as to receive N-PAM symbols when the PAM mode is the first PAM mode and is configured to operate so as to receive M-PAM symbols when the PAM mode is the second PAM mode.

19. The multi-mode PAM receiver of claim 14, wherein the receiver circuit is configured to disable a portion of the receiver circuit when the PAM mode is the first PAM mode.

20. The multi-mode PAM receiver of claim 15, wherein the receiver circuit includes a reflection cancellation equalizer circuit having a delay circuit configured to have a first symbol length when the PAM mode is the first PAM mode and to have a second symbol length when the PAM mode is the second PAM mode.

21. The multi-mode PAM receiver of claim 20, wherein the first symbol length is longer than the second symbol length.

22. The multi-mode PAM receiver of claim 20, wherein the first symbol length is twice the second symbol length.

23. The multi-mode PAM receiver of claim 15, wherein the receiver circuit and multiplexer circuitry are configured such that a total data rate of the multi-mode PAM receiver is the same for the first PAM mode and the second PAM mode.

24. The multi-mode PAM receiver of claim 14,

further comprising an interface configured to receive a byte length mode signal specifying a byte length mode;

wherein the multiplexer circuitry is further configured to order the data from the data stream in accordance with the byte length mode.

25. The multi-mode PAM receiver of claim 24, including a clock circuit configured to generate a byte clock signal from the receive clock signal, the byte clock signal having a clock rate determined, at least in part, by the byte length mode.

26. The multi-mode PAM receiver of claim 14,

further comprising an interface configured to receive a byte length mode signal specifying a byte length mode;

wherein the multiplexer circuitry, when the PAM mode is a first predefined PAM mode, is configured to order the data from the data stream in accordance with the byte length mode.

27. The multi-mode PAM receiver of claim 26, including a clock circuit configured to generate a byte clock signal from the receive clock signal, the byte clock signal having a clock rate determined, at least in part, by the byte length mode.

28. The multi-mode PAM receiver of claim 14, wherein the receiver circuit comprises a first receiver subcircuit and a second receiver subcircuit, each of the first and the second receiver subcircuits configured to output one or more signals.

29. The multi-mode PAM receiver of claim 28,

wherein the signals output by the first receiver subcircuit represent a sequence of most significant bits (MSB) corresponding to the sequence of symbols;

and

wherein the signals output by the second receiver subcircuit represent a sequence of least significant bits (LSB) corresponding to the sequence of symbols.

30. The multi-mode PAM receiver of claim 28, wherein the receiver circuit is configured to disable the second receiver subcircuit when the PAM mode is a first predefined PAM mode.

31. A multi-mode PAM transceiver comprising:

a multi-mode PAM output driver, configured to output a first sequence of symbols and to receive a PAM mode signal specifying a PAM mode;

a multi-mode PAM receiver, configured to receive a second sequence of symbols and to receive the PAM mode signal;

wherein the first sequence of symbols includes an N-PAM symbol when the PAM mode is a first PAM mode;

wherein the first sequence of symbols includes an M-PAM symbol when the PAM mode is a second PAM mode;

wherein N is not equal to M.

32. The multi-mode PAM transceiver of claim 31, wherein the multi-mode PAM output driver and multi-mode PAM receiver are embodied on a single integrated circuit.

33. The multi-mode PAM transceiver of claim 31, wherein the multi-mode PAM output driver and multi-mode PAM receiver are embodied on a single printed circuit board.

34. The multi-mode PAM transceiver of claim 31,

wherein the first sequence of symbols is output at a first symbol rate when the PAM mode is a first PAM mode;

wherein the first sequence of symbols is output at a second symbol rate when the PAM mode is a second PAM mode; and

wherein the first symbol rate is greater than the second symbol rate.

35. The multi-mode PAM transceiver of claim 34, wherein N, M, the first symbol rate and the second symbol rate are related in such a way that a data rate of the first sequence of symbols is approximately when the multi-PAM transceiver is in the first PAM mode and when the multi-PAM transceiver is in the second PAM mode.

36. The multi-mode PAM transceiver of claim 34, wherein a ratio between the first symbol rate and the second symbol rate is approximately equal to log₂(M)/log₂(N).

37. The multi-mode PAM transceiver of claim 31, further comprising control circuitry configured to generate the PAM mode signal.

38. The multi-mode PAM transceiver of claim 37, wherein the multi-mode PAM output driver, the multi-mode PAM receiver, and the control circuitry are embodied on a single integrated circuit.

39. The multi-mode PAM transceiver of claim 37, wherein the multi-mode PAM output driver, the multi-mode PAM receiver, and the control circuitry are embodied on a single printed circuit board.

40. The multi-mode PAM transceiver of claim 37,

wherein the control circuitry is coupled to the multi-PAM receiver;

wherein the control circuitry is configured to read, from the multi-PAM receiver, data derived from the second sequence of symbols; and

wherein the control circuitry is further configured to generate the PAM mode signal based, at least in part, on the read data.

41. The multi-mode PAM transceiver of claim 31, further comprising a clock circuit configured to generate an output clock having a clock rate determined by the PAM mode signal.

42. A method of symbol transmission, comprising:

configuring a multi-mode PAM output driver to operate in a specified PAM mode, the specified PAM mode selected from a plurality of predefined PAM modes;

using the multi-mode PAM output driver, outputting a sequence of symbols;

wherein the sequence of symbols includes an N-PAM symbol when the PAM mode is a first PAM mode;

wherein the sequence of symbols includes an M-PAM symbol when the PAM mode is a second PAM mode; and

wherein N is not equal to M.

43. The method of claim 42, wherein M and N are both integers selected from the group consisting of 2, 4, 8, and 16.

44. The method of claim 42, wherein M and N are both integers selected from the group consisting of 2 and 4.

45. A method of data transmission comprising:

operating the multi-mode PAM output driver so as to drive a first sequence of symbols onto a channel at a first symbol rate, the sequence comprising a plurality of symbols, each symbol having a respective level of a predetermined first number of PAM levels;

receiving, at a multi-mode PAM receiver, the first sequence of symbols from the channel;

determining, based on a relationship between the sequence of driven symbols and the sequence of received symbols, a first symbol quality metric;

operating the multi-mode PAM output driver so as to drive a second sequence of symbols onto a channel at a second symbol rate, the sequence comprising a plurality of symbols, each symbol having a respective level of a predetermined second number of PAM levels; and

receiving, at a multi-mode PAM receiver, the second sequence of symbols from the channel;

wherein the predetermined first and second numbers of PAM levels are different.

46. The method of claim 45, wherein the first and second symbol rates are different.

47. The method of claim 45, wherein the first and second symbol rates and first and second numbers of PAM levels are related so that a data rate of the sequence of symbols is constant.

48. The method of claim 45, wherein the second symbol rate is twice the first symbol rate.

49. The method of claim 45,

wherein the first number of PAM levels is denoted by N;

wherein the second number of PAM levels is denoted by M; and

wherein the ratio between the second symbol rate and the first symbol rate is equal to log₂(N)/log₂(M).

50. A method of data transmission comprising:

operating a multi-mode PAM output driver so as to drive a first sequence of symbols at a first symbol rate selected from a plurality of predetermined symbol rates, the sequence comprising a plurality of symbols, each symbol having a respective level of a first number of PAM levels, the first number of PAM levels selected from a plurality of available PAM levels;

receiving at a multi-mode PAM receiver the first sequence of symbols;

determining a first symbol quality metric corresponding to the first symbol rate and to the first number of PAM levels;

operating the multi-mode PAM driver so as to drive a second sequence of symbols at a second symbol rate selected from the plurality of predetermined symbol rates, the second sequence comprising a plurality of symbols, each symbol having a respective level of a second number of PAM levels, the second number of PAM levels selected from the plurality of available PAM levels;

receiving at the multi-mode PAM receiver the second sequence of symbols;

determining second symbol quality metric corresponding to the second symbol rate and to the second level of predetermined number of PAM levels;

based on the first and the second symbol quality metrics, choosing a mode of operation of the system, the mode of operation specified, at least, by a number of PAM levels.

51. The method of claim 50, wherein the symbol quality metrics are bit error rates.

52. The method of claim 50, wherein the symbol quality metrics are voltage margins.

53. The method of claim 50, wherein the symbol quality metrics are timing margins.

54. The method of claim 50, wherein the choosing a mode of operation includes setting a state of a PAM mode signal.

55. A multi-mode PAM transceiver comprising:

means for outputting a first sequence of symbols in accordance with a PAM mode signal specifying a PAM mode;

means for receiving a second sequence of symbols and for receiving the PAM mode signal;

wherein the first sequence of symbols includes an N-PAM symbol when the PAM mode is a first PAM mode;

wherein the first sequence of symbols includes an M-PAM symbol when the PAM mode is a second PAM mode;

wherein N is not equal to M.