Delay locked loop circuitry for clock delay adjustment

• US 7,308,065 B2
• Filed: 04/18/2006
• Issued: 12/11/2007
• Est. Priority Date: 02/06/1997
• Status: Expired due to Fees

• Current Assignee: Rambus Inc.
• Original Assignee: Rambus Inc.
• Inventors: Kim, Jun, Lee, Thomas H., Stark, Donald C., Johnson, Mark G., Lau, Benedict C., Donnelly, Kevin S., Yu, Leung, Chau, Pak Shing, Nguyen, Nhat M., Garlepp, Bruno W., Horowitz, Mark A., Chan, Yiu-Fai, Tran, Chanh Vi
• Primary Examiner(s): Kim; Kevin
• Application Number:
  US11/406,557
• Publication Number:
  US 20060188051A1
• Time in Patent Office: 602 Days
• Field of Search: 375/371, 375/372, 375/373, 327/149, 327/158
• US Class Current: 375/373
• CPC Class Codes: G06F 1/10 Distribution of clock signals , e.g. skew
• CPC Class Codes: G11C 7/22 Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
• CPC Class Codes: G11C 7/222 Clock generating, synchronizing or distributing circuits within memory device
• CPC Class Codes: H03K 2005/00026 controlled by an analog electrical signal, e.g. obtained after conversion by a D/A converter
• CPC Class Codes: H03K 2005/00032 Dc control of switching transistors
• CPC Class Codes: H03K 2005/00052 by mixing the outputs of fixed delayed signals with each other or with the input signal
• CPC Class Codes: H03K 2005/00208 using differential stages
• CPC Class Codes: H03K 5/133 using a chain of active delay devices
• CPC Class Codes: H03K 5/2481 with at least one differential stage
• CPC Class Codes: H03L 7/07 using several loops, e.g. for redundant clock signal generation
• CPC Class Codes: H03L 7/0805 the loop being adapted to provide an additional control signal for use outside the loop
• CPC Class Codes: H03L 7/0814 the phase shifting device being digitally controlled
• CPC Class Codes: H03L 7/0816 the controlled phase shifter and the frequency- or phase-detection arrangement being connected to a common input
• CPC Class Codes: H04L 7/0008 Synchronisation information channels, e.g. clock distribution lines
• CPC Class Codes: H04L 7/0025 interpolation of clock signal
• CPC Class Codes: H04L 7/0037 Delay of clock signal

Abstract

A receiver adapted to be coupled to a data bus and configured to receive data in accordance with a receive clock includes first and second delay-locked loops. The first delay-locked loop is configured to generate a plurality of phase vectors from a first reference clock, and the second delay-locked loop is coupled to the first delay-locked loop and configured to generate the receive clock from at least one phase vector selected from the plurality of phase vectors and a second reference clock.

Claims

1. A delay locked loop circuit, comprising:

a first loop circuit including a first adjustable delay section to provide a first clock signal having a controlled phase relationship with respect to an external clock signal; and

a second loop circuit, coupled to the first loop circuit, the second loop circuit comprising;

a first phase detector to receive an input clock signal and a first feedback clock signal, the first phase detector to provide a signal that is representative of a phase difference between the first feedback clock signal and the input clock signal;

a first control circuit coupled to the first phase detector, the first control circuit to provide a plurality of control signals based on the signal that is representative of the phase difference between the first feedback clock signal and the input clock signal; and

a selection block coupled to the first adjustable delay section, the selection block to adjust a phase of a second clock signal based on the plurality of control signals and the first clock signal, wherein the second clock signal is distinct from the first clock signal and is used to generate the first feedback clock signal.

2. The delay locked loop circuit of claim 1, the first loop circuit further comprising:

a second phase detector to receive the external clock signal and the first clock signal, the second phase detector to output a signal that is representative of a phase difference between the first feedback clock signal and the external clock signal; and

a second control circuit coupled to the second phase detector, the second control circuit to provide a delay adjustment signal that is based on the signal that is representative of the phase difference between the first clock signal and the external clock signal, wherein a delay of the first adjustable delay section is adjusted based on the delay adjustment signal.

3. The delay locked loop circuit of claim 2, the second loop circuit further comprising a second adjustable delay section to receive the second clock signal and provide the first feedback clock signal, wherein a delay of the second adjustable delay section is controlled by the delay adjustment signal.

4. The delay locked loop circuit of claim 3, wherein:

the first adjustable delay section includes a plurality of delay elements, each delay element of the plurality delay elements to provide a phase vector of a plurality of respective phase vectors, wherein the first clock signal is a second feedback clock signal selected from the plurality of phase vectors; and

the selection block includes;

selection circuitry to select a pair of phase vectors, of the plurality of phase vectors, that bracket a phase of the external clock signal; and

interpolator circuitry to interpolate between the pair of phase vectors and provide the second clock signal.

5. The delay locked loop circuit of claim 1, further comprising a buffer, wherein the buffer includes duty cycle correction circuitry to correct a duty cycle of the external clock signal.

6. The delay locked loop circuit of claim 1, further comprising a filter selected from the group consisting of a majority-detector filter and a unanimity-detector filter, the filter to filter the signal so as to reduce loop jitter.

7. A method of operation in a delay locked loop circuit, the method comprising:

generating a first clock signal in a first loop circuit such that the first clock signal includes a controlled phase relationship with respect to an external clock signal; and

in a second loop circuit coupled to the first loop circuit;

comparing a phase of an input clock signal to a phase of a feedback clock signal to provide a signal that is representative of a phase difference between the feedback clock signal and the input clock signal;

generating a plurality of control signals based on the signal that is representative of the phase difference between the feedback clock signal and the input clock signal; and

adjusting a phase of a second clock signal based on the plurality of control signals and the first clock signal, wherein the second clock signal is distinct from the first clock signal and is used to generate the feedback clock signal.

8. The method of claim 7, further comprising:

in the first loop circuit, performing a comparison between the external clock signal and the first clock signal to output a signal that is representative of a phase difference between the first clock signal and the external clock signal; and

generating a delay adjustment signal that is based on the signal that is representative of the phase difference between the first clock signal and the external clock signal; and

wherein generating the first clock signal includes adjusting a delay of the first clock signal relative to the external clock signal based on the delay adjustment signal.

9. The method of claim 8, further comprising varying a delay of a second adjustable delay section that receives the second clock signal and provides the feedback clock signal, wherein the delay of the second adjustable delay section is controlled by the delay adjustment signal.

10. The method of claim 7, wherein the first clock signal is a first vector and the method further comprises generating a plurality of phase vectors in addition to the first vector;

and

adjusting the phase of the second clock signal further comprises;

selecting a pair of phase vectors of the plurality of phase vectors that bracket a phase of the internal clock signal; and

interpolating between the pair of phase vectors to generate the second clock signal.

11. The method of claim 7, further comprising performing duty cycle correction on the external clock signal.

12. The method of claim 7, further comprising filtering the signal to reduce loop jitter.

13. An integrated circuit memory device, comprising:

a first loop circuit including a first adjustable delay section to provide a first clock signal having a controlled phase relationship with respect to an external clock signal;

a second loop circuit including a selection block coupled to the first adjustable delay section, the selection block to adjust a phase of a second clock signal based on the first clock signal and a phase difference between a first feedback clock signal and an input clock signal, wherein the second clock signal is distinct from the first clock signal and is used to generate the first feedback clock signal; and

a transmitter circuit to output data on both edges of the second clock signal.

14. The integrated circuit memory device of claim 13, the second loop circuit further including:

a first phase detector to receive the input clock signal and the first feedback clock signal, the first phase detector to provide a signal that is representative of the phase difference; and

a first control circuit coupled to the first phase detector, the first control circuit to provide a plurality of control signals based on the signal.

15. The integrated circuit memory device of claim 14, the first loop circuit further including:

a second phase detector, the second phase detector to receive the external clock signal and the first clock signal, the second phase detector to output a signal that is representative of a phase difference between the first clock signal and the external clock signal; and

a second control circuit coupled to the second phase detector, the second control circuit to provide a delay adjustment signal that is based on the signal that is representative of the phase difference between the first clock signal and the external clock signal, wherein a delay of the first adjustable delay section is adjusted based on the delay adjustment signal.

16. The integrated circuit memory device of claim 15, the second loop circuit further including a second adjustable delay section to receive the first clock signal and provide the first feedback clock signal, wherein a delay of the second adjustable delay section is controlled by the delay adjustment signal.

17. The integrated circuit memory device of claim 16, wherein the second adjustable delay section includes a plurality of delay elements, each delay element of the plurality delay elements to provide a phase vector of a plurality of respective phase vectors, wherein the second clock signal is selected from the plurality of phase vectors, the selection circuitry is to select a pair of phase vectors, of the plurality of phase vectors, that bracket a phase of the external clock signal, and wherein the selection block further includes interpolator circuitry to interpolate between the pair of phase vectors and provide the second clock signal.

18. The integrated circuit memory device of claim 13, the first loop circuit further including a buffer, wherein the buffer includes duty cycle correction circuitry to correct a duty cycle of the external clock signal.

19. The integrated circuit memory device of claim 13, the second loop circuit further including a filter to filter a signal that is representative of the phase difference so as to reduce loop jitter, the filter selected from the group consisting of a majority-detector filter and a unanimity-detector filter.