Method of managing a multi-bit cell flash memory with improved reliablility and performance

• US 7,308,525 B2
• Filed: 03/28/2005
• Issued: 12/11/2007
• Est. Priority Date: 01/10/2005
• Status: Active Grant

• Current Assignee: Western Digital Israel Limited (Western Digital Corporation)
• Original Assignee: SanDisk IL Ltd. (Western Digital Corporation)
• Inventors: Lasser, Menahem, Murin, Mark
• Primary Examiner(s): Sparks, Donald
• Assistant Examiner(s): DILLER, JESSE DAVID
• Application Number:
  US11/090,177
• Publication Number:
  US 20060155919A1
• Time in Patent Office: 988 Days
• Field of Search: 711/103, 365/185.33, 365/185.03
• US Class Current: 711/103
• CPC Class Codes: G11C 11/5621 using charge storage in a floating gate
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 2211/5641 Multilevel memory having cells with different number of storage levels

Abstract

A method of storing data by providing a flash memory device including a plurality of memory cells; each of the memory cells is capable of storing data bits. First data bits are stored into memory cells used for storing M bits per cell, the memory cells are allocated to a page of the memory. Second data bits are stored into other memory cells, the other memory cells used for storing N bits per cell are allocated to the page and upon storing of the first data bits and upon storing the second data bits, the page uses at the same time at least one of the memory cells with M bits per cell and at least one of the other memory cells with N bits per cell with N less than M.

Claims

1. A method of storing data, the method comprising the steps of:

(a) providing a flash memory device including a single flash memory die including a plurality of memory cells, wherein each of said memory cells is capable of storing a plurality of data bits;

(b) storing first data bits into at least one of said memory cells, said at least one memory cell allocated to at least one page and said at least one memory cell used for storing M bits per cell; and

(c) storing second data bits into at least one other of said memory cells, said at least one other cell allocated to said at least one page, and said at least one other memory cell used for storing N bits per cell;

wherein said storing first data bits and said storing second data bits are performed at the same time using the same at least one writing operation, wherein N is less than M.

2. The method, according to claim 1, wherein said first data bits are user data bits.

3. The method, according to claim 1, wherein said second data bits are control data bits.

4. The method, according to claim 1, wherein N is selected from the group of integers consisting of one and two.

5. The method, according to claim 1, wherein N equals one, and wherein M equals an integer selected from the group of integers consisting of two, three and four.

6. The method, according to claim 1, wherein N equals two and wherein M equals an integer selected from the group of integers consisting of three and four.

7. The method, according to claim 1, wherein said at least one writing operation is executed with a single write command.

8. The method, according to claim 1, further comprising the step of:

(d) reading said at least one memory cell and said at least one other memory cell in a single read operation, wherein said reading reads at least one of said first data bits and at least one of said second data bits.

9. The method, according to claim 1, further comprising the step of:

(d) reading said at least one other memory cell in a single read operation, wherein said reading reads at least one of said second data bits.

10. The method, according to claim 1, wherein said at least one other memory cell uses an available voltage state of largest voltage.

11. The method, according to claim 1, wherein said at least one other memory cell uses an available voltage state other than the voltage state of largest voltage used by said at least one memory cell.

12. The method, according to claim 1, wherein said at least one other memory cell uses an available voltage state of second largest voltage.

13. The method, according to claim 1, wherein said flash memory device is a NAND flash memory device.

14. A method of reading stored data, the method comprising the steps of:

(a) providing a flash memory device including a single flash memory die including a plurality of memory cells, wherein each of said memory cells is capable of storing M data bits, wherein M is an integer greater than one; and

b) reading in a single command a single bit respectively from each of said memory cells of a page, wherein said single bit read from one of said memory cells is valid only when less than M bits are stored in said one memory cell.

16. The method, according to claim 14, wherein M is an integer selected from the group consisting of two, three and four.

15. A method of reading stored data, the method comprising the steps of:

(a) providing a flash memory device including a single flash memory die including a plurality of memory cells, wherein each of said memory cells is capable of storing M data bits, wherein M is an integer greater than one; and

(b) providing a read command for reading a group of said cells, wherein said read command always performs a single voltage comparison on each said memory cell of said group.

17. A flash memory device comprising:

(a) a plurality of memory cells in a single flash memory die, wherein each of said memory cells is capable of storing a plurality of data bits; and

(b) a controller which stores first data bits in at least one of said memory cells said at least one cell storing M bits per cell; and

second data bits in at least one other of said memory cells, said at least one other cell storing N bits per cell;

wherein said at least one memory cell is allocated to at least one page, wherein said at least one other cell is allocated to said at least one page, wherein the same at least one writing operation is used for storing at the same time M bits per cell in at least one of said memory cells and N bits per cell in at least one of said other memory cells, wherein N is less than M.

18. The flash memory device, according to claim 17, wherein said first data bits are user data bits.

19. The flash memory device, according to claim 17, wherein said second data bits are control data bits.

20. The flash memory device, according to claim 17, wherein N is selected from the group of integers consisting of one and two.

21. The flash memory device, according to claim 17, wherein N equals one, and wherein M equals an integer selected from the group of integers consisting of two, three and four.

22. The flash memory device, according to claim 17, wherein N equals two and wherein M equals an integer selected from the group of integers consisting of three and four.

23. The flash memory device, according to claim 17, wherein said at least one writing operation is executed with a single write command.

24. The flash memory device, according to claim 17, wherein said controller reads at least one of said second data bits with a single read operation.

25. The flash memory device, according to claim 17, wherein said controller stores at least one said second data bits using an available voltage state of largest voltage.

26. The flash memory device, according to claim 17, wherein said at least one other memory cell uses an available voltage state other than the voltage state of largest voltage used by said at least one memory cell.

27. A flash memory device comprising:

(a) a plurality of memory cells in a single flash memory die, wherein each of said memory cells is capable of storing M data bits, wherein M is an integer greater than one; and

b) a mechanism for reading in a single command a single bit respectively from any of said memory cells of a page, wherein said single bit read from one of said memory cells is valid only when less than M bits are stored in said one memory cell.

28. The flash memory device, according to claim 27, wherein M is an integer selected from the group consisting of two, three and four.

29. A flash memory device comprising:

(a) a plurality of memory cells in a single flash memory die, wherein each of said memory cells is capable of storing M data bits, wherein M is an integer greater than one; and

(b) a mechanism for providing a read command for reading a group of said cells wherein said read command always performs a single voltage comparison on each said memory cell of said group.

30. The flash memory device, according to claim 29, wherein M is an integer selected from the group consisting of two, tree and four.

31. A method of storing data, the method comprising the steps of

(a) providing a flash memory device including a single flash die including a plurality of memory cells, wherein each of said memory cells is capable of being put into any one of a plurality of cell states;

(b) storing first data bits into at least one of said memory cells, said at least one memory cell allocated to at least one page, and said storing first data bits making use of M of said plurality of cell states;

(c) storing second data bits into at least one other of said memory cells, said at least one other memory cell allocated to said at least one page, and said storing second data bits making use of N of said plurality of cell states; and

wherein said storing first data bits and said storing second data bits is performed at the same time using the same at least one writing operation, and wherein N is less than M.