Concurrent read access and exclusive write access to data in shared memory architecture

• US 7,308,539 B2
• Filed: 12/17/2004
• Issued: 12/11/2007
• Est. Priority Date: 12/17/2004
• Status: Active Grant

• Current Assignee: Lenovo International Limited (Lenovo Group Ltd.)
• Original Assignee: International Business Machines Corporation
• Inventors: Fuhs, Ronald Edward, Haraden, Ryan Scott, Sellin, Nathaniel Paul, Willenborg, Scott Michael
• Primary Examiner(s): Kim, Hong
• Assistant Examiner(s): Ayash, Marwan
• Application Number:
  US11/016,218
• Publication Number:
  US 20060136677A1
• Time in Patent Office: 1,089 Days
• Field of Search: 711/168, 711/141
• US Class Current: 711/141
• CPC Class Codes: G06F 12/0831 using a bus scheme, e.g. with bus monitoring or watching means
• CPC Class Codes: G06F 12/0835 for main memory peripheral accesses (e.g. I/O or DMA)
• CPC Class Codes: G06F 12/0875 with dedicated cache, e.g. instruction or stack

Abstract

Concurrent read access and exclusive write access are provided in a shared memory architecture to permit one or more devices in the shared memory architecture to maintain read access to a block of memory such as a cache line while one device has exclusive permission to modify that block of memory. By doing so, a device that has permission to modify may make updates to its copy of the block of memory without invalidating other copies of the block of memory, and potentially enabling other devices to continue to read data from their respective copies of the block of memory without having to retrieve the updated copy of the block of memory.

Claims

1. A method of maintaining coherence between a plurality of devices coupled to a shared memory architecture, the method comprising:

in a first device, retrieving a first copy of a block of memory and obtaining exclusive write access to the block of memory;

in a second device, retrieving a second copy of the block of memory and obtaining read access to the block of memory, wherein the second device has read access to the block of memory concurrently with the first device having exclusive write access to the block of memory;

modifying the first copy of the block of memory in the first device while the second device has read access to the block of memory;

using data in the second copy of the block of memory in the second device after the first copy of the block of memory has been modified and while the first device has exclusive write access to the block of memory; and

after using the data in the second copy of the block of memory, updating the second copy of the block of memory based upon the first copy of the block of memory in the first device;

wherein the first device comprises a receiver circuit and the second device comprises a transmitter circuit, the transmitter and receiver circuits respectively configured to transmit and receive packets of data arranged in a sequence, with each packet associated with a packet identifier, wherein the block of memory includes a last acknowledged packet identifier representing a last packet for which an acknowledgment has been received.

2. The method of claim 1, wherein the block of memory comprises a cache line.

3. The method of claim 1, wherein the receiver circuit is configured to update the last acknowledged packet identifier in connection with receiving an acknowledgment packet, and wherein the transmitter circuit is configured to use the data in the second copy of the block of memory by comparing the last acknowledged packet identifier stored in the second copy of the block of memory with a next send packet identifier, and to update the second copy of the block of memory based upon the first copy of the block of memory in the first device by requesting the first copy of the block of memory from the receiver circuit to update the last acknowledge packet identifier in the transmitter circuit.

4. A method of maintaining coherence between a plurality of devices coupled to a shared memory architecture, the method comprising:

in a first device, retrieving a first copy of a block of memory and obtaining exclusive write access to the block of memory;

in a second device, retrieving a second copy of the block of memory and obtaining read access to the block of memory, wherein the second device has read access to the block of memory concurrently with the first device having exclusive write access to the block of memory; and

respectively accessing data in the first and second copies of the block of memory with the first and second devices while the second device has read access to the block of memory concurrently with the first device having exclusive write access to the block of memory;

modifying the first copy of the block of memory in the first device while the second device has read access to the block of memory;

using data in the second copy of the block of memory in the second device after the first copy of the block of memory has been modified and while the first device has exclusive write access to the block of memory;

and after using the data in the second copy of the block of memory, updating the second copy of the block of memory based upon the first copy of the block of memory in the first device;

wherein the first device comprises a receiver circuit and the second device comprises a transmitter circuit, the transmitter and receiver circuits respectively configured to transmit and receive packets of data arranged in a sequence, with each packet associated with a packet identifier, wherein the block of memory includes a last acknowledged packet identifier representing a last packet for which an acknowledgment has been received.

5. The method of claim 4, wherein obtaining exclusive write access comprises transitioning the block of memory to a shared with permission to modify state.

6. The method of claim 4, wherein obtaining exclusive write access in the first device is performed after obtaining read access in the second device and without invalidating the second copy of the block of memory in the second device.

7. The method of claim 4, further comprising, updating the second copy of the block of memory in the second device by retrieving the first copy of the block of memory from the first device.

8. The method of claim 4, wherein the block of memory comprises a cache line.

9. The method of claim 4, further comprising:

in the receiver circuit, updating the last acknowledged packet identifier in connection with receiving an acknowledgment packet; and

in the transmitter circuit, using the data in the second copy of the block of memory by comparing the last acknowledged packet identifier stored in the second copy of the block of memory with a next send packet identifier, and updating the second copy of the block of memory based upon the first copy of the block of memory in the first device by requesting the first copy of the block of memory from the receiver circuit to update the last acknowledge packet identifier in the transmitter circuit.

10. A circuit arrangement configured for use in a shared memory architecture, the circuit arrangement comprising:

a first device configured to retrieve a first copy of a block of memory and obtain exclusive write access to the block of memory; and

a second device configured to retrieve a second copy of the block of memory and obtain read access to the block of memory, wherein the second device has read access to the block of memory concurrently with the first device having exclusive write access to the block of memory;

wherein the first device is configured to modify the first copy of the block of memory while the second device has read access to the block of memory;

wherein the second device is configured to use data in the second copy of the block of memory after the first copy of the block of memory has been modified and while the first device has exclusive write access to the block of memory, and after using the data in the second copy of the block of memory, update the second copy of the block of memory based upon the first copy of the block of memory in the first device;

wherein the first device comprises a receiver circuit and the second device comprises a transmitter circuit, the transmitter and receiver circuits respectively configured to transmit and receive packets of data arranged in a sequence, with each packet associated with a packet identifier, wherein the block of memory includes a last acknowledged packet identifier representing a last packet for which an acknowledgment has been received.

11. The circuit arrangement of claim 10, wherein the first device is configured to obtain exclusive write access by transitioning the block of memory to a shared with permission to modify state.

12. The circuit arrangement of claim 10, wherein the first device is configured to obtain exclusive write access in the first device after the second device obtains read access and without invalidating the second copy of the block of memory in the second device.

13. The circuit arrangement of claim 10, wherein the second device is further configured to update the second copy of the block of memory by retrieving the first copy of the block of memory from the first device.

14. The circuit arrangement of claim 10, wherein the block of memory comprises a cache line.

15. The circuit arrangement of claim 10, wherein the receiver circuit is configured to update the last acknowledged packet identifier in connection with receiving an acknowledgment packet, and wherein the transmitter circuit is configured to use the data in the second copy of the block of memory by comparing the last acknowledged packet identifier stored in the second copy of the block of memory with a next send packet identifier, and to update the second copy of the block of memory based upon the first copy of the block of memory in the first device by requesting the first copy of the block of memory from the receiver circuit to update the last acknowledge packet identifier in the transmitter circuit.

16. An integrated circuit device comprising the first and second devices of claim 10.

17. A computer comprising the first and second devices of claim 10.