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Fast, scalable pattern-matching engine

  • US 7,308,561 B2
  • Filed: 12/12/2003
  • Issued: 12/11/2007
  • Est. Priority Date: 12/12/2003
  • Status: Expired due to Fees
First Claim
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1. A system for detecting a pattern in a data stream comprising:

  • a FIFO for receiving an N-bit wide data stream and a corresponding first clock signal at a first rate, and outputting the data stream as a W times N-bit wide data stream and a corresponding second clock signal at a second rate, where W is an integer natural number and the second rate equals the first rate divided by W;

    a bus splitter for splitting the W times N-bit wide data stream into W data streams of width N;

    a plurality (W) of RAMs, each RAM for storing data obtained by processing the pattern and for receiving a respective one of the data streams of width N as an address and the second clock signal as a clock, and each RAM being operable to output a portion of the data on an M-bit wide output bus in accordance with a value of the address;

    a processor for receiving the portions of data on each M-bit wide output bus as data and the second clock signal as a clock, and being operable to determine whether the pattern is in the data stream in dependence upon the received portions of data and the received clock, and for outputting a pattern match signal indicating detection of the pattern in the data stream; and

    a channel state RAM for storing the state of the processor and running C times slower the data rate.

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