Apparatus and method for calibration of a temperature sensor

• US 7,309,157 B1
• Filed: 09/28/2004
• Issued: 12/18/2007
• Est. Priority Date: 09/28/2004
• Status: Active Grant

• Current Assignee: National Semiconductor Corporation (Texas Instruments, Inc.)
• Original Assignee: National Semiconductor Corporation (Texas Instruments, Inc.)
• Inventors: Aslan, Mehmet, Tam, Eric, Ren, Qing Feng, D'Aquino, Dan, Ng, Chungwai Benedict
• Primary Examiner(s): VERBITSKY, GAIL KAPLAN
• Application Number:
  US10/952,514
• Time in Patent Office: 1,176 Days
• Field of Search: 374/170, 374/171, 374/172, 374/178, 374/1, 374/183, 327512-513, 702/130, 702/133, 702/99
• US Class Current: 374/178
• CPC Class Codes: G01K 15/00 Testing or calibrating of thermometers
• CPC Class Codes: G01K 7/01 using semiconducting elements having PN junctions G01K7/02, G01K7/16, G01K7/30 take precedence

Abstract

A circuit for temperature sensing provides a bias current to a PN junction, and the PN junction provides a PN junction voltage in response to the bias current. Also, a parasitic resistance may be coupled in series with the PN junction. The circuit for temperature sensing is configured to determine the temperature of the PN junction based on the PN junction voltage. Further, the circuit includes registers which store ηtrim, which is based on the difference between the non-ideality of the PN junction used from a reference PN junction; ΔI, which is based on the difference between a reference bias current and the bias current for the part; Rtrim, which is based the parasitic resistance; and Ntrim, which includes other offsets. The registers may be set during trimming and/or calibration to provide accurate temperature sensing for the parameters employed.

Claims

1. A method for temperature sensing, comprising:

providing a bias current to a temperature sensor that includes at least one PN junction;

providing a diode non-ideality signal that is based on a non-ideality of the at least one PN junction and a non-ideality of a reference PN junction; and

providing a digital signal that indicates a temperature of the temperature sensor, based, in part, on a PN junction voltage received from the temperature sensor in response to the bias current, and further based on the diode non-ideality signal such that the digital signal is substantially scaled according to the diode non-ideality signal.

2. A method for temperature sensing, comprising:

providing a bias current to a PN junction, wherein a parasitic resistance is coupled in series with the PN junction;

providing a current-dependent offset cancellation signal having a value that is substantially equal to Δ

I*Rtrim, wherein Δ

I represents a difference between the bias current and a reference bias current; and

wherein Rtrim is based, in part, on the parasitic resistance; and

providing a digital signal that indicates a temperature of the PN junction, based, in part, on a voltage of the PN junction; and

further based on the current-dependent offset cancellation signal such that the digital signal is substantially offset by Δ

I*Rtrim.

3. The method of claim 2, further comprising:

providing another offset cancellation signal, wherein providing the digital signal is further accomplished such that the digital signal is further based on said another offset cancellation signal such that digital signal is substantially offset by a total offset of Δ

I*Rtrim+Ntrim, where Ntrim represents a value of said another offset cancellation signal.

4. The method of claim 2, wherein Rtrim is substantially equal to Rs*G, where Rs represents the parasitic resistance, G represents a gain factor that is substantially given by G=q/(η

0*k*ln(M)), η

0 represents the non-ideality factor of a reference PN junction, k represents Boltzmann'"'"'s constant, q represents the charge of an electron, and M represents a ratio that is associated with the PN junction voltage.

5. The method of claim 2, further comprising:

providing a non-ideality signal having a non-ideality value that is based on a non-ideality of the PN junction, wherein providing the digital signal is further accomplished such that at least a non-offset portion of the digital signal is substantially proportional to the non-ideality value.

6. The method of claim 2, wherein providing the current-dependent offset cancellation signal is accomplished by:

storing a current offset value that corresponds to Δ

I;

storing a resistor trim value that corresponds to Rtrim; and

providing the current-dependent offset value based on the stored current offset value and the stored resistor value.

7. The method of claim 2, wherein providing the digital signal is accomplished by:

sampling the PN junction voltage a plurality of times;

providing the bias current such that the bias current corresponds to a first current during a portion of the plurality of times, and corresponds to a second current during a another portion of the plurality of times, wherein the ratio of the first current to the second current is M;

1;

each of the plurality of times that the PN junction voltage is sampled;

receiving a measured voltage that substantially corresponds to the PN junction voltage plus a voltage that is associated with the parasitic resistance;

performing analog processing on the measured voltage to provide a processed PN junction voltage; and

converting the processed PN junction voltage into a digital sampled value; and

after sampling the PN junction voltage a plurality of times, providing the digital signal based on each of the digital sampled values.

8. The method of claim 7, wherein providing the digital signal is accomplished substantially according to the equation:

Tmeas=q*Δ

VBE/(η

0*k*ln(M))−

Δ

I*Rtrim, where Tmeas represents a value of the digital signal, Δ

VBE represents the difference in the PN junction voltage during the portion of the plurality of times and the PN junction voltage during other portion of the plurality of times, η

0 represents the non-ideality factor of a reference PN junction, k represents Boltzmann'"'"'s constant, and q represents the charge of an electron.

9. The method of claim 7, further comprising:

providing a non-ideality signal having a non-ideality value that is based on a non-ideality of the PN junction, wherein providing the digital signal is further accomplished such that at least a non-offset portion of the digital signal is substantially proportional to the non-ideality value; and

providing another offset cancellation signal, wherein providing the digital signal is further accomplished such that the digital signal is further based on the other offset cancellation signal such that digital signal is substantially offset by a total offset of Δ

I*Rs+Ntrim, where Ntrim represents a value of the other offset cancellation signal, and wherein providing the digital signal is accomplished substantially according to the equation;

Tmeas=η

trim*[q*Δ

VBE/(η

0*k*ln(M))]−

Δ

I*Rtrim−

Ntrim, where Tmeas represents a value of the digital signal;

Δ

VBE represents a difference in the PN junction voltage during the portion of the plurality of times and the PN junction voltage during other portion of the plurality of times;

η

0 represents a non-ideality factor of a reference PN junction, k represents Boltzmann'"'"'s constant;

q represents the charge of an electron; and

η

trim represents a value of the non-ideality signal, wherein the value of the non-ideality signal is substantially equal to a ratio of the non-ideality of the PN junction to the non-ideality of the reference PN junction, and wherein Rtrim is substantially equal to Rs*η

trim*[q/(η

0*k*ln(M))], where Rs represents the parasitic resistance.

10. A circuit for temperature sensing, comprising:

a temperature measurement circuit that is arranged to provide a digital signal that indicates a temperature of a temperature sensor that includes at least one PN junction, based, in part, on a PN junction voltage of the temperature sensor; and

further based on a diode non-ideality signal such that the digital signal is substantially scaled according to the diode non-ideality signal; and

a memory component that is configurable to store a diode non-ideality value that is based on a non-ideality of the at least one PN junction and a non-ideality of a reference PN junction, and arranged to provide the diode non-ideality signal based on the diode non-ideality value.

11. The circuit of claim 10, wherein the temperature measurement circuit includes a bias current source that is configured to provide a bias current to the temperature sensor, the memory component is a first register that is configurable to store the diode non-ideality value, and wherein the circuit for temperature sensing further comprises:

a second register that is configurable to store a resistor value that corresponds to Rtrim, wherein Rtrim is based, in part, on a parasitic resistance that is coupled in series with the at least one PN junction; and

a third register that stores a current offset value that corresponds to Δ

I, wherein Δ

I represents a difference between the bias current and a reference current, and wherein the temperature measurement circuit is arranged to provide the digital signal such that the PN junction is further based on the resistor value and the current offset value such that the digital signal is substantially offset by Δ

I*Rtrim.

12. The circuit of claim 11, further comprising:

A fourth register that stores another offset value, wherein the temperature measurement circuit is arranged to provide the digital signal such that the digital signal is further based on said another offset value such that a total offset of the digital signal is substantially given by Δ

I*Rtrim+Ntrim, where Ntrim represents the other offset value.

13. The circuit of claim 10, wherein the temperature measurement circuit includes a bias current source that is configured to provide a bias current to the PN junction, and wherein the temperature measurement circuit further includes:

a control circuit; and

a converter circuit, including;

an analog front-end processing circuit that is arranged to receive a measured voltage that substantially corresponds to the PN junction voltage, and further arranged to provide a processed signal from the measured PN junction voltage; and

an analog-to-digital converter circuit that is arranged to convert the processed signal into a digital sampled value, wherein the digital signal is based, in part, on the digital sampled value.

14. The circuit of claim 13, wherein at least one of the bias current circuit source, the analog front-end processing circuit, and the analog-to-digital converter circuit is arranged to provide a gain that is based on the non-ideality signal to provide the substantial scaling of the digital signal.

15. The circuit of claim 13, wherein the converter circuit further includes a digital processing component, wherein the digital processing component is arranged to provide the digital signal based, in part, on the digital sampled value, the digital processing component is arranged to provide a gain that is based on the diode non-ideality value to provide the substantial scaling of the digital signal, and wherein the diode non-ideality value corresponds to a ratio of the non-ideality of the at least one PN junction to the non-ideality of the reference PN junction.

16. The circuit of claim 13, wherein the temperature measurement circuit is configured to provide the digital signal by performing actions, including:

sampling the PN junction voltage a plurality of times; and

controlling the PN junction voltage such that a difference of the PN junction voltage during a portion of the plurality of times to the PN junction voltage during another portion of the plurality of times is substantially given by ln(M)*η

*k*T/q, where M represents a pre-determined number, η

represent a non-ideality of the PN junction, k represents Boltzmann'"'"'s constant, T represents the absolute temperature of the PN junction, and q represents the charge of an electron.

17. The circuit of claim 16, wherein

the bias current source is arranged to provide the bias current such that the bias current corresponds to a first current if a current control signal corresponds to a first value, and such that the bias current corresponds to a second current if the current control signal corresponds to the second value, wherein a ratio of the first current to the second current is M:

1;

and wherein the control circuit is arranged to control the PN junction voltage by providing the current control signal such that the bias current corresponds to the first current during the portion of the plurality of times, and corresponds to a second current during the other portion of the plurality of times.

18. The circuit of claim 16, wherein the temperature measurement circuit is configured to control the PN junction voltage by providing the bias current to a first PN junction of the at least one PN junction during the plurality of times and providing the bias current to a second PN junction of the at least one PN junction during the other plurality of times, wherein the ratio of the area of the first PN junction to the area of the second PN junction is substantially equal to M:

1.

19. The circuit of claim 16, wherein temperature measurement circuit is configured to provide the digital signal according to the equation:

Tmeas=Δ

VBE*G, where Tmeas represents a value of the digital signal;

Δ

VBE represents the difference in the PN junction voltage during the portion of the plurality of times and the PN junction voltage during other portion of the plurality of times;

G is substantially given by G=GA*GAD*GD, GA represents a gain provided by the analog front-end processing circuit;

GAD represents a gain provided by the analog-to-digital conversion circuit;

GD represents gain applied after the analog-to-digital conversion, if any; and

G is one of predetermined and adjusted such that G is substantially given by;

G=η

trim*[q/(η

0*k*ln(M))], where η

0 represents a non-ideality of a reference PN junction, and η

trim represents the diode non-ideality value, wherein the diode non-ideality value is substantially equal to a ratio of the non-ideality of the PN junction to the non-ideality of the reference PN junction.

20. The circuit of claim 16, further comprising:

a second register that is configurable to store a resistor value that corresponds to Rtrim, wherein Rtrim is based, in part, on a parasitic resistance that is coupled in series with the PN junction; and

a third register that stores a current offset value that corresponds to Δ

I, wherein Δ

I represents a difference between the bias current and a reference current, and wherein the temperature measurement circuit is arranged to provide the digital signal such that the PN junction is further based on the resistor value and the current offset value;

a fourth register that stores another offset value, wherein the analog-to-digital converter circuit includes a sigma-delta analog-to-digital converter circuit that is arranged to perform an analog-to-digital conversion on the processed signal;

the temperature measurement circuit is arranged to provide the digital signal such that the digital signal is further based on the other offset value such that a total offset of the digital signal is substantially given by Δ

I*Rtrim+Ntrim, where Ntrim represents to the other offset value; and

wherein temperature measurement circuit is configured to provide the digital signal according to the equation;

Tmeas=Δ

VBE*(K₀+η

trim)/VREF−

Δ

I*Rtrim−

Ntrim, where Tmeas represents a value of the digital signal;

Δ

VBE represents the difference in the PN junction voltage during the portion of the plurality of times and the PN junction voltage during the other portion of the plurality of times;

η

trim represents the diode non-ideality value;

VREF represents a reference voltage; and

K₀ is substantially pre-determined according to the equation;

K₀=VREF*q/(η

0*k*ln(M)),

where η

0 represents the non-ideality factor of the reference PN junction, wherein the control circuit is arranged to control the sigma-delta analog-to-digital converter circuit such that K₀+η

trim clock cycles are employed during one of the analog-to-digital conversion and an oversampling of the PN junction voltage, wherein η

trim is pre-determined substantially according to the equation;

η

trim=VREF*q/(η

0*k*ln(M))−

K₀,

and wherein Rtrim is pre-determined substantially according to the equation;

Rtrim=Rs*(K₀+η

trim)/VREF.