Quasi self-aligned source/drain FinFET process

• US 7,309,626 B2
• Filed: 11/15/2005
• Issued: 12/18/2007
• Est. Priority Date: 11/15/2005
• Status: Expired due to Fees

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: International Business Machines Corporation
• Inventors: Ludwig, Thomas, Nowak, Edward J., Ouyang, Qiqing C., Ieong, Mei-Kei
• Primary Examiner(s): VU, HUNG K
• Application Number:
  US11/164,215
• Publication Number:
  US 20070108536A1
• Time in Patent Office: 763 Days
• Field of Search: 438/149, 438/157, 438/164, 438/176, 438/283, 438/479, 438/515, 438/517
• US Class Current: 438/157
• CPC Class Codes: H01L 21/845 including field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 27/1211 combined with field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/66818 the channel being thinned after patterning, e.g. sacrificial oxidation on fin
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

A method of forming a semiconductor structure including a plurality of finFFET devices in which crossing masks are employed in providing a rectangular patterns to define relatively thin Fins along with a chemical oxide removal (COR) process is provided. The present method further includes a step of merging adjacent Fins by the use of a selective silicon-containing material. The present invention also relates to the resultant semiconductor structure that is formed utilizing the method of the present invention.

Claims

1. A method of forming a semiconductor structure comprising:

providing a structure including a plurality of patterned material stacks comprising a nitride layer on top of an oxide hardmask on a surface of semiconductor substrate and a plurality of patterned photomasks which cross over said plurality of patterned material stacks;

performing a chemical oxide removal step that laterally etches at least exposes sidewalls of said oxide hardmask of each material stack not protected by one of said patterned photomasks;

removing the plurality of patterned photomasks to expose patterned material stacks including a laterally etched oxide hardmask beneath said nitride layer;

performing an anisotropic etching process selective to the laterally etched oxide hardmask to remove said nitride layer and at least an upper portion of any semiconducting material of said semiconductor substrate not protected by said laterally etched oxide hardmask thereby forming Fins; and

forming a plurality of gate regions that cross over said Fins.

2. The method of claim 1 further comprising forming a Si-containing material between each of said Fins so as to join adjoining Fins.

3. The method of claim 2 wherein said Si-containing material comprises one of single crystalline Si, SiGe or SiGeC.

4. The method of claim 1 wherein said semiconductor substrate is an SOI or bulk semiconductor.

5. The method of claim 1 wherein said chemical oxide removal step comprises utilizing a gaseous or vaporous mixture of HF and ammonia, wherein the ratio of HF to ammonia is from about 1:

10 to about 10;

1.

6. The method of claim 1 further comprising removing said laterally etched oxide hardmask exposing upper portions of the semiconducting material of the semiconductor substrate previously protected by said laterally etched oxide hardmask.

7. The method of claim 1 wherein each Fin has wider end portions relative to its middle portion, and said gate regions are formed so as to cross said middle portion, and source/drain regions are formed within said wider end portions.

8. The method of claim 1 further comprising forming source/drain regions within end portions of each Fin, said end portions of each Fin are substantially square.

9. A method of forming a semiconductor structure comprising:

providing a plurality of patterned material stacks comprising a nitride layer on top of an oxide hardmask on a surface of top semiconducting layer of an SOI substrate and a plurality of patterned photomasks which cross over said plurality of patterned material stacks;

performing a chemical oxide removal step which laterally etches at least exposes sidewalls said oxide hardmask of each material stack not protected by one of said patterned photomasks;

removing the plurality of patterned photomasks to expose patterned material stacks including a laterally etched oxide hardmask beneath said nitride layer;

performing an anisotropic etching process selective to the laterally etched oxide hardmask to remove said nitride layer and at least said top semiconducting layer of the SOI substrate not protected by said laterally etched oxide hardmask, stopping on a buried insulating layer of said SOI substrate;

removing said laterally etched oxide hardmask exposing upper portions of the top semiconducting layer of the SOI substrate previously protected by said laterally etched oxide hardmask as well as exposed portions of the buried insulating layer, wherein portions of said exposed top semiconducting layer of the SOI substrate previously protected by said laterally etched oxide hardmask defines Fins; and

forming a plurality of gate regions which cross over said Fins.

10. The method of claim 9 further comprising forming a Si-containing material between each of said Fins so as to join adjoining Fins.

11. The method of claim 9 wherein said chemical oxide removal step comprises utilizing a gaseous or vaporous mixture of HF and ammonia, wherein the ratio of HF to ammonia is from about 1:

10 to about 10;

1.