Semiconductor device capable of preventing current flow caused by latch-up and method of forming the same

• US 7,309,883 B2
• Filed: 04/01/2004
• Issued: 12/18/2007
• Est. Priority Date: 05/02/2003
• Status: Expired due to Term

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Ahn, Soon-Hong, Lee, Jung-Hwa
• Primary Examiner(s): Le, Thao X.
• Application Number:
  US10/815,448
• Publication Number:
  US 20040217427A1
• Time in Patent Office: 1,356 Days
• Field of Search: 257370-373, 257/361, 257/497, 257/378, 257/173, 257/355, 257/E27.063, 257/E21.061
• US Class Current: 257/173
• CPC Class Codes: H01L 21/823878 isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
• CPC Class Codes: H01L 21/823892 with a particular manufacturing method of the wells or tubs, e.g. twin tubs, high energy well implants, buried implanted layers for lateral isolation [BILLI]
• CPC Class Codes: H01L 27/0921 Means for preventing a bipolar, e.g. thyristor, action between the different transistor regions, e.g. Latchup prevention

Abstract

A semiconductor device includes first, second, and third wells. The first well is connected to a pad to which an external pin is connected and includes a first-type diffusion region that receives a well bias voltage. The second well is adjacent to the first well, and includes an insulating region and a second-type diffusion region outside the insulating region. The third well is adjacent to the second well and includes a first-type diffusion region that receives a first voltage. The insulating region inside the second well along with the first-type well diffusion region of the first well constitute a bipolar junction transistor that cuts off current flowing from the first well to the third well.

Claims

1. A semiconductor device comprising:

a first well connected to a pad to which an external pin is connected, the first well including a first-type diffusion region connected to a bias voltage terminal;

a second well adjacent to the first well, the second well including an insulating region having a first-type diffusion region and at least one second-type diffusion region outside the insulating region, wherein the at least one second-type diffusion region of the second well is connected to a first voltage terminal, and wherein the first-type diffusion region of the insulating region is connected to a second voltage terminal; and

a third well adjacent to the second well and including a first-type diffusion region connected to the first voltage terminal,

wherein the insulating region inside the second well, the at least one second-type diffusion region of the second well, and the first-type diffusion region of the first well, constitute a bipolar junction transistor which operates in a cut-off mode to cut off current from flowing from the first well to the third well when a control voltage is applied to the second voltage terminal.

2. The semiconductor device of claim 1, wherein the at least one second-type diffusion region outside the insulating region comprises a first second-type diffusion region and a second second-type diffusion region, and the second well comprises:

a first sub-well arranged between the insulating region and the first well and including the first second-type diffusion region; and

a second sub-well arranged between the insulating region and the third well and including the second second-type diffusion region,

wherein the insulating region is a third sub-well having the first-type diffusion region.

3. The semiconductor device of claim 2, wherein the first and second sub-wells of the second well are P-wells, and the second-type diffusion regions of the first and second sub-wells of the second well are each connected to the first voltage terminal.

4. The semiconductor device of claim 2, wherein the third sub-well is an N-well.

5. The semiconductor device of claim 4, wherein a voltage applied to the first voltage terminal is a ground voltage, and the control voltage generates a backward voltage between a base and an emitter of a bipolar junction transistor, the bipolar junction transistor comprising the first-type diffusion region of the first well, the second-type diffusion region of the first sub-well, and the first-type diffusion region of the third sub-well.

6. The semiconductor device of claim 1, wherein the first and third wells are N-wells.

7. The semiconductor device of claim 1, wherein the well bias voltage applied to the first-type diffusion region of the first well is a power supply voltage.

8. The semiconductor device of claim 1, wherein a region to which the pad is connected is a second-type diffusion region.

9. The semiconductor device of claim 1, wherein the first-type diffusion regions are formed of N-type impurities, and the at least one second-type diffusion region is formed of P-type impurities.

10. The semiconductor device of claim 1, wherein the insulating region of the second well has a structure that surrounds the first well.

11. The semiconductor device of claim 1, wherein the third well constitutes a depletion-type MOS transistor.

12. A semiconductor device comprising:

a first N-well connected to a pad to which an external pin is connected, the first N-well including an N-type diffusion region connected to a bias voltage terminal, and a P-type diffusion region formed in the vicinity of the pad;

a first P-well adjacent to the first N-well, the first P-well including an insulating region and at least one P-type diffusion region outside the insulating region, the at least one P-type diffusion region of the first P-well outside of the insulating region is connected to a first voltage terminal; and

a second N-well adjacent to the first P-well and including an N-type diffusion region connected to the first voltage terminal,

wherein the insulating region is a sub-N-well embedded within said first P-well and having an N-type diffusion region connected to a second voltage terminal for receiving an off mode control voltage for preventing a latch-up current.

13. The semiconductor device of claim 12, wherein the at least one P-type diffusion region comprises a first P-type diffusion region and a second P-type diffusion region and the first P-well comprises:

a first sub-P-well located between the insulating region and the first N-well and including the first P-type diffusion region; and

a second sub-P-well located between the insulating region and the second N-well and including the second P-type diffusion region.

14. The semiconductor device of claim 13, wherein the N-type diffusion region of the first N-well, the P-type diffusion region of the first sub-P-well, and the N-type diffusion region of the insulating region constitute a bipolar junction transistor which cuts off a current flowing from the first N-well to the second N-well.

15. The semiconductor device of claim 14, wherein the control voltage provided to the second voltage terminal generates a backward voltage between a base and an emitter of the bipolar junction transistor composed of the N-type diffusion region of the first N-well, the P-type diffusion region of the first sub-P-well, and the N-type diffusion region of the insulating region.

16. The semiconductor device of claim 12, wherein the bias voltage terminal connected to the N-type diffusion region of the first N-well is adapted to receive a power supply voltage for the semiconductor device.

17. The semiconductor device of claim 12, wherein the insulating region of the first P-well has a structure that surrounds the first N-well.

18. The semiconductor device of claim 12, wherein the second N-well constitutes a depletion-type MOS transistor.

19. A method of forming a semiconductor device comprising:

forming a first well connected to a pad to which an external pin is connected, the first well including a first-type diffusion region connected to a bias voltage terminal;

forming a second well adjacent to the first well, the second well including an insulating region having a first-type diffusion region and at least one second-type diffusion region outside the insulating region, wherein the at least one second-type diffusion region of the second well is connected to a first voltage terminal, and the first-type diffusion region of the insulating region is connected to a second voltage terminal; and

forming a third well adjacent to the second well and including a first-type diffusion region connected to the first voltage terminal,

wherein the insulating region inside the second well, the at least one second-type diffusion region of the second well outside of the insulating region and the first-type diffusion region of the first well constitute a bipolar junction transistor which operates in a cut-off mode to cut off current flowing from the first well to the third well when a control voltage is applied to the second voltage terminal.

20. The method of claim 19, wherein the at least one second-type diffusion region outside the insulating region comprises a first second-type diffusion region and a second second-type diffusion region, and the step of forming a second well comprises:

forming a first sub-well between the insulating region and the first well, the first sub-well including the first second-type diffusion region; and

forming a second sub-well between the insulating region and the third well, the second sub-well including the second second-type diffusion region,

wherein the insulating region is a third sub-well having the first-type diffusion region.

21. The method of claim 20, wherein the first and second sub-wells of the second well are P-wells, and the second-type diffusion regions of the first and second sub-wells of the second well are each connected to the first voltage terminal.

22. The method of claim 20, wherein the third sub-well is an N-well.

23. The method of claim 19, wherein the first and third wells are N-wells.

24. The method of claim 19, wherein the first-type diffusion regions are formed of N-type impurities, and the at least one second-type diffusion region is formed of P-type impurities.