Chip structure and process for forming the same

• US 7,309,920 B2
• Filed: 05/06/2005
• Issued: 12/18/2007
• Est. Priority Date: 12/21/1998
• Status: Expired due to Fees

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Megica Corporation (Chipbond Technology Corporation)
• Inventors: Lin, Mou-Shiung, Lee, Jin-Yuan, Huang, Ching-Cheng
• Primary Examiner(s): Jackson; Jerome
• Assistant Examiner(s): Chu; Chris C.
• Application Number:
  US11/123,936
• Publication Number:
  US 20050263893A1
• Time in Patent Office: 956 Days
• Field of Search: 257/E27.014, 257/E29.054, 257/758, 257/528, 257/362, 257/368, 257/529, 257/E21.575, 257/E21.579, 257/298, 257/300, 257/303, 257/306, 257/309, 365/185.01
• US Class Current: 257/758
• CPC Class Codes: H01L 21/768 Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
• CPC Class Codes: H01L 21/76807 for dual damascene structures
• CPC Class Codes: H01L 21/76838 characterised by the formation and the after-treatment of the conductors etching for patterning the conductors H01L21/3213
• CPC Class Codes: H01L 21/76885 By forming conductive members before deposition of protective insulating material, e.g. pillars, studs
• CPC Class Codes: H01L 2224/0231 Manufacturing methods of the redistribution layers
• CPC Class Codes: H01L 2224/02311 Additive methods
• CPC Class Codes: H01L 2224/02313 Subtractive methods
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/04042 Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
• CPC Class Codes: H01L 2224/05548 Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/13 of an individual bump connector
• CPC Class Codes: H01L 2224/13099 Material
• CPC Class Codes: H01L 23/522 including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
• CPC Class Codes: H01L 23/5222 Capacitive arrangements or effects of, or between wiring layers other capacitive arrangements H01L23/642
• CPC Class Codes: H01L 23/5223 Capacitor integral with wiring layers
• CPC Class Codes: H01L 23/5227 Inductive arrangements or effects of, or between, wiring layers other inductive arrangements H01L23/645
• CPC Class Codes: H01L 23/5228 Resistive arrangements or effects of, or between, wiring layers other resistive arrangements H01L23/647
• CPC Class Codes: H01L 23/5286 Arrangements of power or ground buses
• CPC Class Codes: H01L 23/5329 Insulating materials
• CPC Class Codes: H01L 23/53295 Stacked insulating layers
• CPC Class Codes: H01L 23/60 : Protection against electrostatic charges or discharges, e.g. Faraday shields
• CPC Class Codes: H01L 24/02 : Bonding areas on insulating substrates, e.g. chip carriers, H01L23/49816, H01L23/49838, H01L23/5389; Manufacturing methods related thereto
• CPC Class Codes: H01L 24/05 : of an individual bonding area
• CPC Class Codes: H01L 24/10 : Bump connectors bumps on insulating substrates, e.g. chip carriers, H01L23/49816; Manufacturing methods related thereto
• CPC Class Codes: H01L 24/11 : Manufacturing methods for bumps on insulating substrates H01L21/4853
• CPC Class Codes: H01L 24/13 : of an individual bump connector
• CPC Class Codes: H01L 27/0251 : for MOS devices
• CPC Class Codes: H01L 27/0676 : comprising combinations of diodes, or capacitors or resistors
• CPC Class Codes: H01L 27/08 : including only semiconductor components of a single kind
• CPC Class Codes: H01L 28/10 : Inductors
• CPC Class Codes: H01L 28/20 : Resistors
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01015 : Phosphorus [P]
• CPC Class Codes: H01L 2924/01019 : Potassium [K]
• CPC Class Codes: H01L 2924/01022 : Titanium [Ti]
• CPC Class Codes: H01L 2924/01023 : Vanadium [V]
• CPC Class Codes: H01L 2924/01024 : Chromium [Cr]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/04953 : TaN
• CPC Class Codes: H01L 2924/12044 : OLED
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/15174 : in different layers of the multilayer substrate
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/30105 : Capacitance
• CPC Class Codes: Y10T 29/49124 : On flat or curved insulated base, e.g., printed circuit, etc.
• CPC Class Codes: Y10T 29/49204 : Contact or terminal manufacturing

Abstract

A chip or wafer comprises a semiconductor substrate, first and second transistors on the semiconductor substrate, first and second metal layers over the semiconductor substrate, an insulating layer on the first and second metal layers, a third and fourth metal layers on the insulating layer, a passivation layer over the third and fourth metal layers, and a fifth metal layer over the passivation layer. A signal is suited to be transmitted from the first transistor to the second transistor sequentially through the first, third, fifth, fourth and second metal layers.

Claims

1. A chip, comprising:

a silicon substrate;

a first transistor in or on said silicon substrate;

a second transistor in or on said silicon substrate;

a first interconnecting structure over said silicon substrate, wherein said first interconnecting structure comprises a first portion and a second portion over said first portion, wherein said first portion is connected to said second portion;

a second interconnecting structure over said silicon substrate, wherein said second interconnecting structure comprises a third portion and a fourth portion over said third portion, wherein said third portion is connected to said fourth portion, wherein said first interconnecting structure is separate from said second interconnecting structure, wherein said first and third portions are provided by a first metal layer, and said second and fourth portions are provided by a second metal layer over said first metal layer;

an insulating layer between said first and second metal layers;

a passivation layer over said first and second interconnecting structures and over said insulating layer, wherein said passivation layer comprises a topmost nitride layer of said chip, wherein a first opening in said passivation layer exposes a first pad of said first interconnecting structure, and a second opening in said passivation layer exposes a second pad of said second interconnecting structure, wherein said first opening has a width between 0.5 and 20 micrometers; and

a third interconnecting structure over said passivation layer and over said first and second pads, wherein said first transistor is connected to said second transistor through, in sequence, said first interconnecting structure, said first opening, said third interconnecting structure, said second opening and said second interconnecting structure, wherein said third interconnecting structure comprises a metal line having a thickness greater than 1 micrometer and greater than those of said first and second metal layers, and having a width greater than 1 micrometer.

2. The chip of claim 1, wherein said third interconnecting structure comprises gold.

3. The chip of claim 1, wherein said third interconnecting structure comprises copper.

4. The chip of claim 1, wherein said third interconnecting structure comprises aluminum.

5. The chip of claim 1 further comprising a polymer layer over said third interconnecting structure.

6. The chip of claim 1 further comprising a polymer layer over said passivation layer, wherein said third interconnecting structure comprises a third metal layer and a fourth metal layer over said third metal layer, wherein said polymer layer is between said third and fourth metal layers.

7. The chip of claim 1 further comprising a polymer layer between said passivation layer and said third interconnecting structure.

18. The chip of claim 1, wherein said third interconnecting structure comprises nickel.

19. The chip of claim 1, wherein said third interconnecting structure comprises an electroplated metal.

20. The chip of claim 1, wherein said third interconnecting structure comprises titanium.

8. A wafer, comprising:

a silicon substrate;

a first transistor in or on said silicon substrate;

a second transistor in or on said silicon substrate;

a first interconnecting structure over said silicon substrate, wherein said first interconnecting structure comprises a first portion and a second portion over said first portion, wherein said first portion is connected to said second portion;

a second interconnecting structure over said silicon substrate, wherein said second interconnecting structure comprises a third portion and a fourth portion over said third portion, wherein said third portion is connected to said fourth portion, wherein said first interconnecting structure is separate from said second interconnecting structure, wherein said first and third portions are provided by a first metal layer, and said second and fourth portions are provided by a second metal layer over said first metal layer;

an insulating layer between said first and second metal layers;

a passivation layer over said first and second interconnecting structures and over said insulating layer, wherein said passivation layer comprises a topmost nitride layer of said wafer, wherein a first opening in said passivation layer exposes a first pad of said first interconnecting structure, and a second opening in said passivation layer exposes a second pad of said second interconnecting structure, wherein said first opening has a width between 0.5 and 20 micrometers;

a first polymer layer over said passivation layer, wherein a third opening in said first polymer layer exposes said first pad, and a fourth opening in said first polymer layer exposes said second pad, wherein said first polymer layer has a thickness greater than those of said insulating layer and said passivation layer; and

a third interconnecting structure over said first polymer layer and over said first and second pads, wherein said first transistor is connected to said second transistor through, in sequence, said first interconnecting structure, said third opening, said third interconnecting structure, said fourth opening and said second interconnecting structure, wherein said third interconnecting structure comprises a metal line having a thickness greater than 1 micrometer and greater than those of said first and second metal layers, and having a width greater than 1 micrometer.

9. The wafer of claim 8, wherein said third interconnecting structure comprises gold.

10. The wafer of claim 8, wherein said third interconnecting structure comprises copper.

11. The wafer of claim 8, wherein said third interconnecting structure comprises aluminum.

12. The wafer of claim 8 further comprising forming a second polymer layer over said third interconnecting structure.

13. The wafer of claim 8 further comprising a second polymer layer over said passivation layer, wherein said third interconnecting structure comprises a third metal layer and a fourth metal layer over said third metal layer, wherein said polymer layer is between said third and fourth metal layers.

14. The wafer of claim 8, wherein said third opening further exposes said passivation layer.

15. The wafer of claim 8, wherein said third interconnecting structure comprises nickel.

16. The wafer of claim 8, wherein said third interconnecting structure comprises an electroplated metal.

17. The wafer of claim 8, wherein said third interconnecting structure comprises titanium.