Semiconductor integrated circuit

• US 7,310,006 B2
• Filed: 11/16/2005
• Issued: 12/18/2007
• Est. Priority Date: 11/17/2004
• Status: Expired due to Fees

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: NEC Electronics Corporation (Renesas Electronics Corporation)
• Inventors: Shimada, Eiji
• Primary Examiner(s): CHANG, DANIEL D
• Application Number:
  US11/274,184
• Publication Number:
  US 20060103428A1
• Time in Patent Office: 762 Days
• Field of Search: 326/17, 326/82, 326/83, 327/108, 327/110, 327/309, 327/314
• US Class Current: 326/83
• CPC Class Codes: H03K 17/063 in field-effect transistor switches
• CPC Class Codes: H03K 17/0822 in field-effect transistor switches
• CPC Class Codes: H03K 2017/0806 against excessive temperature

Abstract

To provide an output MOS transistor from breaking due to dump surge and counter electromotive, a semiconductor integrated circuit according to an embodiment of the invention includes an output MOS transistor controlling current flowing through a load, a dynamic clamp circuit clamping an overvoltage applied to the output MOS transistor, a delay circuit generating a reference signal by adjusting a level of a gate voltage of the output MOS transistor, and a clamp controlling circuit making the dynamic clamp circuit operate based on the reference signal when a counter electromotive force is applied to the output MOS transistor.

Claims

1. A semiconductor integrated circuit connected between a power supply and an inductive load, comprising:

an output transistor controlling current flowing through the inductive load;

a clamp circuit clamping an overvoltage applied to the output transistor;

a reference signal generator circuit generating a reference signal by adjusting a level of a control signal input to a control electrode of the output transistor, said reference signal generator circuit comprising one of a time delay function and a hysteresis function; and

a clamp controlling circuit bringing the clamp circuit into operation based on the reference signal on condition that a counter electromotive force of the inductive load is applied to the output transistor.

2. The semiconductor integrated circuit according to claim 1, wherein the clamp controlling circuit inactivates the clamp circuit on condition that a dump surge of the power supply is applied to the output transistor.

3. The semiconductor integrated circuit according to claim 1, wherein the reference signal generator circuit gives a delay to the control signal to adjust a level of the control signal at a predetermined timing.

4. The semiconductor integrated circuit according to claim 3, wherein the reference signal generator circuit comprises a CR integrating circuit including a resistor element and a capacitor element.

5. The semiconductor integrated circuit according to claim 1, wherein the reference signal generator circuit decreases the control signal by a first level on a rising edge of the control signal, and increases the control signal by a second level on a falling edge of the control signal.

6. The semiconductor integrated circuit according to claim 5, wherein the reference signal generator circuit includes a first diode element decreasing the control signal by the first level and a second diode element increasing the control signal by the second level.

7. The semiconductor integrated circuit according to claim 5, wherein the reference signal generator circuit includes a first transistor decreasing the control signal by the first level and a second transistor increasing the control signal by the second level.

8. A semiconductor integrated circuit, comprising:

a high-side switching circuit driving an inductive load;

a control signal generator circuit generating a control signal controlling a driving operation of the high-side switching circuit, said control signal generator circuit comprising one of a time delay function and a hysteresis function;

a discharging circuit discharging the control signal to the inductive load under an off-state of the high-side switching circuit; and

a counter electromotive force protective circuit protecting the high-side switching circuit from a counter electromotive force based on a reference signal obtained by decreasing slope of a rising edge or a falling edge of the control signal.

9. A semiconductor integrated circuit, comprising:

an output transistor connected between a power supply terminal supplied with power and an output terminal connected with an inductive load and operating in response to a control signal applied to a control terminal thereof;

a clamp circuit connected between the control terminal and the power supply terminal;

a reference signal generator circuit generating a reference signal by changing a level of the control signal, said reference signal generator circuit comprising one of a time delay function and a hysteresis function; and

a clamp controlling circuit connected between the power supply terminal and the output terminal, and controlling an operation of the clamp circuit in accordance with the reference signal.

10. The semiconductor integrated circuit according to claim 9, wherein the clamp circuit includes:

a high-voltage diode clamping a counter electromotive force applied to the output transistor; and

a backflow preventive diode preventing a current backflow from the control terminal to the power supply terminal.

11. The semiconductor integrated circuit according to claim 9, wherein the clamp controlling circuit includes:

a first clamp controlling transistor connected between the power supply terminal and the output terminal, and operating in response to the reference signal;

a clamp controlling resistor series-connected with the first clamp controlling transistor; and

a second clamp controlling transistor series-connected with the clamp circuit, and operating in response to a signal at a node between the clamp controlling resistor and the first clamp controlling transistor.

12. The semiconductor integrated circuit according to claim 9, wherein the reference signal generator circuit includes a resistor element and a capacitor element which are series-connected between the control terminal and the output terminal, and the reference signal is a signal at a node between the resistor element and the capacitor element.

13. The semiconductor integrated circuit according to claim 9, wherein the reference signal generator circuit includes a first diode element and a second diode element connected in parallel and in reverse direction between the control terminal and a reference signal input terminal of the clamp controlling circuit.

14. The semiconductor integrated circuit according to claim 9, wherein the reference signal generator circuit includes a first reference signal generating transistor and a second reference signal generating transistor which are parallel-connected between the control terminal and a reference signal input terminal of the clamp controlling circuit,

the first reference signal generating transistor has a control terminal connected with the reference signal input terminal, and

the second reference signal generating transistor has a control terminal connected with the control terminal of the output transistor.

15. The semiconductor integrated circuit according to claim 9, wherein the output transistor comprises a vertical type MOS transistor.