Efficient graphics pipeline with a pixel cache and data pre-fetching

• US 7,310,100 B2
• Filed: 06/29/2004
• Issued: 12/18/2007
• Est. Priority Date: 12/22/1999
• Status: Expired due to Fees

• Current Assignee: Microsoft Technology Licensing LLC (Microsoft Corporation)
• Original Assignee: Microsoft Corporation
• Inventors: Hussain, Zahid
• Primary Examiner(s): Tung, Kee M.
• Assistant Examiner(s): Nguyen, Hau H
• Application Number:
  US10/879,325
• Publication Number:
  US 20040233208A1
• Time in Patent Office: 1,267 Days
• Field of Search: 345/506, 345/418, 345/419, 345/545, 345/557, 345537-538, 345/547, 345/660, 345/552, 345/422, 711/118, 711/169
• US Class Current: 345/557
• CPC Class Codes: G06T 1/20 Processor architectures; Processor configuration, e.g. pipelining
• CPC Class Codes: G06T 1/60 Memory management

Abstract

An efficient graphics pipeline with a pixel cache and data pre-fetching. By combining the use of a pixel cache in the graphics pipeline and the pre-fetching of data into the pixel cache, the graphics pipeline of the present invention is able to take best advantage of the high bandwidth of the memory system while effectively masking the latency of the memory system. More particularly, advantageous reuse of pixel data is enabled by caching, which when combined with pre-fetching masks the memory latency and delivers high throughput. As such, the present invention provides a novel and superior graphics pipeline over the prior art in terms of more efficient data access and much greater throughput. In one embodiment, the present invention is practiced within a computer system having a processor for issuing commands; a memory sub-system for storing information including graphics data; and a graphics sub-system for processing the graphics data according to the commands from the processor. The graphics sub-system comprises a rasterizer for traversing graphics primitives of the graphics data to generate pixel coordinates for pixels corresponding to the graphics primitives; a graphics pipeline for processing the graphics data of the pixels; and a pixel cache for caching the pixel data. In this embodiment, he graphics sub-system masks the inherent latency of the memory sub-system by pre-fetching the graphics data and storing the graphics data within the pixel cache.

Claims

1. A method for processing graphics data in a graphics pipeline of a computer system, said graphics data comprising color data, stencil z-buffer data, and texture data, said graphics pipeline comprising a color pipeline for processing the color data, the stencil z-buffer pipeline for processing the stencil z-buffer data, and the texture pipeline for processing the texture data, said method comprising the steps of:

a) storing said graphics data within a memory sub-system of said computer system, said memory sub-system having an inherent memory latency;

b) traversing graphics primitives of said graphics data to generate pixel coordinates for pixels corresponding to said graphics primitives;

c) generating cache addresses for said pixels based on said pixel coordinates;

d) pre-fetching said graphics data such that said graphics data is retrieved from said memory sub-system before said graphics data is needed; and

e) storing said graphics data at said cache addresses within a color cache coupled to the color pipeline and dedicated for use by the color pipeline, a stencil z-buffer cache coupled to the stencil z-buffer pipeline and dedicated for use by the stencil z-buffer pipeline, and a texture cache coupled to the texture pipeline and dedicated for use by the texture pipeline such that said graphics data is immediately available when needed despite said inherent memory latency of said memory sub-system.

2. The method as recited in claim 1, further comprising, the step of storing said cache addresses in a pre-fetch queue.

3. The method as recited in claim 1, further comprising the step of storing said pixel coordinates in said pre-fetch queue.

4. The method as recited in claim 1, wherein said pre-fetch queue stores said cache addresses in a first-in first-out (FIFO) manner.

5. The method as recited in claim 1, wherein said at least one of said caches comprises a write-back cache.

6. The method as recited in claim 1, wherein at least one of said caches comprises a set-associative cache.

7. The method as recited in claim 1, wherein at least one of said caches comprises cache lines that are organized as two-dimensional (2-D) arrays.

8. The method as recited in claim 1, further comprising the step of displaying graphics images according to said pixel data on a display.

9. The method as recited in claim 1, wherein at least one of said caches is organized such that primitives that are spatially located proximate each other are located proximate each other in the pixel cache and thereby improving pixel cache hit rate.

10. The method as recited in claim 1, further comprising the step of generating appropriated sized tiles of pixel data for storage in at least one of said caches.

11. The method as recited in claim 1, wherein at least one of said caches comprises a hierarchy of tiles of pixels.

12. A system for processing graphics data comprising color data, stencil z-buffer data, and texture data, the system comprising:

a graphics pipeline comprising a color pipeline for processing the color data, a stencil z-buffer pipeline for processing the stencil z-buffer data, and a texture pipeline for processing the texture data;

a memory sub-system in communication with the graphics pipeline for storing graphics data, the communication between the memory sub-system and the graphics pipeline having an inherent memory latency;

a set of caches comprising a color cache coupled to the color pipeline and dedicated for use by the color pipeline, a stencil z-buffer cache coupled to the stencil z-buffer pipeline and dedicated for use by the stencil z-buffer pipeline, and a texture cache coupled to the texture pipeline and dedicated for use by the texture pipeline;

wherein the system pre-fetches the graphics data from the memory sub-system to said caches such that the graphics data is retrieved from said memory sub-system and stored in said caches before the graphics data is desired by the graphics pipeline such that the graphics data is immediately available to the graphics pipeline despite the inherent memory latency of the memory sub-system and wherein cache addresses for said caches are generated based on pixel coordinates.

13. The system as recited in claim 12, further comprising a pre-fetch queue coupled to at least one of said caches.

14. The system as recited in claim 13, wherein the pre-fetch queue comprises a first-in first-out pre-fetch queue.

15. The system as recited in claim 13, wherein the pre-fetch queue stores pixel coordinates.

16. The system as recited in claim 13, wherein the pre-fetch queue stores said cache addresses.

17. The system as recited in claim 12, wherein at least one of said caches comprises a write-back cache.

18. The system as recited in claim 12, wherein at least one of said caches comprises a set-associative cache.

19. The system as recited in claim 12, wherein at least one of said caches comprises cache lines that are organized as two-dimensional (2-D) arrays.

20. The system as recited in claim 12, wherein at least one of said caches is organized such that primitives that are spatially located proximate each other are located proximate each other in the pixel cache and thereby improving pixel cache hit rate.

21. The system as recited in claim 12, wherein the system generates appropriated sized tiles of pixel data for storage in at least one of said caches.

22. The system as recited in claim 12, wherein at least one of said caches comprises a hierarchy of tiles of pixels.