Imaging device with boosting circuit

• US 7,310,115 B2
• Filed: 03/28/2003
• Issued: 12/18/2007
• Est. Priority Date: 03/29/2002
• Status: Active Grant

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Sanyo Electric Company Limited (Panasonic Holdings Corporation)
• Inventors: Tanimoto, Takashi
• Primary Examiner(s): Ye, Lin
• Assistant Examiner(s): Bemben, Richard M
• Application Number:
  US10/402,193
• Publication Number:
  US 20030193574A1
• Time in Patent Office: 1,726 Days
• Field of Search: 348/312, 348/372, 348/207.99, 348/222.1
• US Class Current: 348/372
• CPC Class Codes: H04N 23/651 for reducing power consumption by affecting camera operations, e.g. sleep mode, hibernation mode or power off of selective parts of the camera
• CPC Class Codes: H04N 25/70 SSIS architectures; Circuits associated therewith
• CPC Class Codes: H04N 25/709 Circuitry for control of the power supply
• CPC Class Codes: H04N 25/71 Charge-coupled device [CCD] sensors; Charge-transfer registers specially adapted for CCD sensors
• CPC Class Codes: H04N 25/75 Circuitry for providing, modifying or processing image signals from the pixel array

Abstract

An imaging device that is activated quickly and prevents deterioration of an image signal. The imaging device includes a boosting circuit for boosting an input voltage to generate a boosted voltage. A solid state imaging device receives the boosted voltage and generates the image signal. A clock signal generation unit is connected to the boosting circuit to determine a timing for generating the image signal in correspondence with a vertical synchronization signal and a horizontal synchronization signal and to generate a boosting clock signal for operating the boosting circuit. The clock signal generation unit continuously generates the boosting clock signal during a predetermined period in which the imaging operation starts and, after the predetermined period, generates the boosting clock signal during at least part of a blanking period of the vertical synchronization signal and the horizontal synchronization signal.

Claims

1. An imaging device for performing an imaging operation to generate an image signal, the imaging device comprising:

a boosting circuit for boosting an input voltage to generate a boosted voltage;

a solid state imaging device connected to the boosting circuit to receive the boosted voltage and generate the image signal;

a drive circuit connected to the boosting circuit and the solid state imaging device to generate a drive clock signal with the boosted voltage, wherein the drive circuit provides the solid state imaging device with the drive clock signal to generate the image signal;

a clock signal generation unit connected to the boosting circuit to determine a timing for generating the image signal in correspondence with a vertical synchronization signal and a horizontal synchronization signal and to generate a boosting clock signal for operating the boosting circuit, wherein there is a blanking period for the vertical and horizontal synchronization signals, wherein the clock signal generation unit includes,

a boosting clock signal generation circuit for generating the boosting clock signal, the boosting clock signal generation circuit generating the boosting clock signal during the blanking period of one of the vertical synchronization signal and the horizontal synchronization signal, and

a timing signal generation circuit coupled to the drive circuit, for providing a timing signal that sets a timing for providing the solid state imaging device with the drive clock signal from the drive circuit; and

a control circuit connected to the clock signal generation circuit and the timing signal generation circuit, for controlling the clock signal generation circuit to continuously generate a plurality of boosting clock signals during a predetermined period after the imaging operation starts and before the blanking period, wherein the predetermined period is longer than the blanking period of the vertical synchronization signal or the horizontal synchronization signal, and wherein the control circuit controls the timing signal generation circuit to start providing the drive circuit with the timing signal when the predetermined period has elapsed.

2. The imaging device according to claim 1, wherein the clock signal generation unit includes

a counter connected to the boosting clock signal generation circuit to count the number of clock pulses of the boosting clock signal and generate a count value;

wherein the control circuit is also connected to the counter to compare the count value with a predetermined target value and to change a generation mode of the boosting clock signal in accordance with the comparison result.

3. The imaging device according to claim 2,

wherein the control circuit controls the timing signal generation circuit to start providing the drive circuit with the timing signal when the count value reaches the predetermined target value.

4. The imaging device according to claim 1, wherein the clock signal generation unit includes:

a comparator for comparing the boosted voltage with a predetermined reference voltage to generate a comparison signal; and

a control circuit connected to the comparator and the boosting clock signal generation circuit to change a generation mode of the boosting clock signal with the boosting clock signal generation circuit in accordance with the comparison signal.

5. The imaging device according to claim 4, further comprising:

wherein the timing signal generation circuit starts providing the drive circuit with the timing signal when the boosted voltage reaches the predetermined reference voltage.

6. An imaging device having a standby mode and an imaging mode, the imaging device comprising:

a boosting circuit for boosting an input voltage to generate a boosted voltage;

a solid state imaging device connected to the boosting circuit to receive the boosted voltage and generate the image signal;

a drive circuit connected to the boosting circuit and the solid state imaging device to generate a drive clock signal with the boosted voltage, wherein the drive circuit provides the solid state imaging device with the drive clock signal to generate the image signal;

a clock signal generation unit connected to the boosting circuit to determined a timing for generating the image signal in correspondence with a vertical synchronization signal and a horizontal synchronization signal and to generate a boosting clock signal for operating the boosting circuit, wherein there is a blanking period for the horizontal and vertical synchronization signals, wherein the clock signal generation unit includes,

a boosting clock signal generation circuit for generating the boosting clock signal, the boosting clock signal generation circuit generating the boosting clock signal during the blanking period of one of the vertical synchronization signal and the horizontal synchronization signal, and

a timing signal generation circuit coupled to the drive circuit, for providing a timing signal that sets a timing for providing the solid state imaging device with the drive clock signal from the drive circuit; and

a control circuit connected to the clock signal generation circuit and the timing signal generation circuit, for controlling the clock signal generation circuit to continuously generate a plurality of boosting clock signals during a predetermined period from when the standby mode is switched to the imaging mode before the blanking period, wherein the predetermined period is longer than the blanking period of the vertical synchronization signal or the horizontal synchronization signal, and wherein the control circuit controls the timing signal generation circuit to start providing the drive circuit with the timing signal when the predetermined period has elapsed.

7. The imaging device according to claim 6, wherein the clock signal generation unit includes

a counter connected to the boosting clock signal generation circuit to count the number of clock pulses of the boosting clock signal from when the standby mode is switched to the imaging mode and generate a count value;

wherein the control circuit is also connected to the counter to stop the continuous generation of the plurality of boosting clock signals and enable the generation of the image signal when the count value reaches a predetermined target value.

8. The imaging device according to claim 6, wherein the clock signal generation unit includes:

a comparator for comparing the boosted voltage with a predetermined reference voltage to generate a comparison signal; and

a control circuit connected to the comparator and the boosting clock signal generation circuit to stop the continuous generation of the boosting clock signal and enable the generation of the image signal in accordance with the comparison signal when the boosted voltage reaches the predetermined reference voltage.

9. A method for controlling an imaging device that performs an imaging operation to generate an image signal, the imaging device including a boosting circuit, which boosts an input voltage in accordance with a boosting clock signal to generate a boosted voltage, and a solid state imaging device, which receives the boosted voltage and generates the image signal in correspondence with a vertical synchronization signal and a horizontal synchronization signal, a drive circuit, which provides the solid state imaging device with a drive clock signal to generate the image signal in response to a timing signal, wherein there is a blanking period for the vertical and horizontal synchronization signals, the method comprising:

validating a start trigger signal to have the imaging device start the imaging operation;

starting continuous generation of a plurality of boosting clock signals when the start trigger signal is validated;

stopping the continuous generation of the plurality of boosting clock signal after a predetermined period from when the start trigger signal is validated, wherein the predetermined period is longer than the blanking period of the vertical synchronization signal or the horizontal synchronization signal;

starting providing the drive circuit with the timing signal when the predetermined period has elapsed; and

after the predetermined period, generating a boosting clock signal during the blanking period of one of the vertical synchronization signal and the horizontal synchronization signal.

10. The method according to claim 9, wherein said stopping the continuous generation of the boosting clock signal includes:

measuring the predetermined period by counting the number of the plurality of boosting clock signals from when the start trigger signal is validated.

11. The method according to claim 9, wherein said stopping the continuous generation of the boosting clock signal includes:

comparing the boosted voltage with a predetermined reference voltage; and

stopping the continuous generation of the boosting clock signal when the boosted voltage reaches the predetermined reference voltage.

12. The method according to claim 9, further comprising:

starting the generation of the image signal after said stopping the continuous generation of the plurality of boosting clock signals.