Non-volatile memory with improved program-verify operations

• US 7,310,255 B2
• Filed: 12/29/2005
• Issued: 12/18/2007
• Est. Priority Date: 12/29/2005
• Status: Active Grant

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: SanDisk Corporation (Western Digital Corporation)
• Inventors: Chan, Siu Lung
• Primary Examiner(s): Elms, Richard T.
• Assistant Examiner(s): Yang, Han
• Application Number:
  US11/323,577
• Publication Number:
  US 20070171725A1
• Time in Patent Office: 719 Days
• Field of Search: 365/185.03, 365/185.22, 365/185.24
• US Class Current: 365/22
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/3454 Arrangements for verifying correct programming or for detecting overprogrammed cells
• CPC Class Codes: G11C 2211/5621 Multilevel programming verification
• CPC Class Codes: G11C 8/08 Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines
• CPC Class Codes: G11C 8/12 Group selection circuits, e.g. for memory block selection, chip selection, array selection

Abstract

In programming a non-volatile memory involving alternately applying a programming pulse and verifying the programming, time is saved in the program verify portion when, depending on the states of the memory cells, a portion of the verify operation is recognized to be superfluous and skipped. Preferably, in a program verify operation relative to a demarcation threshold level for demarcating between two memory states, the verify operation includes a sequence of two verify sub-cycles, the first sub-cycle performing a verify relative to a first threshold level at a predetermined margin below the demarcation threshold level and the second sub-cycle performing a verify relative to a second threshold level which is identical to the demarcation threshold level. Unlike conventional cases, the second sub-cycle is not performed until any one memory cell of the group has been verified to pass the first threshold.

Claims

1. A non-volatile memory, comprising:

an array of memory cells to be programmed relative to a demarcation threshold voltage;

a programming circuit for applying a programming pulse to the group of memory cells;

a sensing circuit with a first configuration to verify the cells of the group relative to a first reference threshold voltage at a predetermined margin below that of the demarcation threshold voltage;

a memory controller;

said controller alternately controlling the operations of the programming circuit and the sensing circuit with the first configuration until one of the cells has been verified relative to the first reference threshold voltage;

a program retardation circuit for slowing down subsequent programming of a memory cell that has been verified to the first reference threshold voltage;

a program inhibit circuit for inhibiting a memory cell that has been verified relative to the demarcation threshold voltage from further programming; and

said controller alternately controlling the operations of the programming circuit and the sensing circuit to verify the cells of the group relative to the first reference threshold voltage followed by verify relative to the demarcation threshold voltage until all cells in the group has been program verified relative to the demarcation threshold voltage.

2. The non-volatile memory as in claim 1, further comprising:

accessing the group of memory cells by associated bit lines; and

wherein

said modifying a programming setup includes raising a voltage on the bit line of the cell that has been verified to the first reference threshold voltage to slow the programming.

3. The non-volatile memory as in claim 1, further comprising:

accessing the group of memory cells by associated bit lines; and

wherein

said program inhibit circuit includes raising the bit line associated with the memory cell to be inhibited substantially to the a supply voltage while the cells not inhibited have their bit lines at substantially zero voltage.

4. The non-volatile memory as in claim 1, wherein said programming pulse is monotonically increasing with every pulse.

5. The non-volatile memory as in claim 1, wherein said group of memory cells is a portion of a flash EEPROM.

6. The non-volatile memory as in claim 1, wherein said group of memory cells is embodied in a memory card.