Access circuit and method for allowing external test voltage to be applied to isolated wells

• US 7,310,259 B2
• Filed: 05/23/2006
• Issued: 12/18/2007
• Est. Priority Date: 12/29/2003
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Zimlich, David A.
• Primary Examiner(s): PHAM, LY D
• Application Number:
  US11/439,635
• Publication Number:
  US 20060221659A1
• Time in Patent Office: 574 Days
• Field of Search: 365/72, 365/191, 365/202, 365/201, 365/175, 365/177, 257/499, 257/544
• US Class Current: 365/72
• CPC Class Codes: G11C 11/401 forming cells needing refreshing or charge regeneration, i.e. dynamic cells
• CPC Class Codes: G11C 29/12005 comprising voltage or current generators
• CPC Class Codes: G11C 29/1201 comprising I/O circuitry
• CPC Class Codes: G11C 29/48 Arrangements in static stores specially adapted for testing by means external to the store, e.g. using direct memory access [DMA] or using auxiliary access paths
• CPC Class Codes: G11C 29/50 Marginal testing, e.g. race, voltage or current testing
• CPC Class Codes: G11C 29/50016 of retention
• CPC Class Codes: G11C 5/066 Means for reducing external access-lines for a semiconductor memory clip, e.g. by multiplexing at least address and data signals
• CPC Class Codes: H01L 27/0222 Charge pumping, substrate bias generation structures
• CPC Class Codes: H10B 12/50 Peripheral circuit region structures

Abstract

An access circuit selectively couples an externally accessible terminal to each of a plurality of isolated DRAM wells in which respective DRAM arrays are fabricated. The access circuit for each well includes first and second transistors fabricated in respective wells coupled between the externally accessible terminal and a respective one of the DRAM wells. The well of the first transistor is coupled to the externally accessible terminal, and the well of the other transistor is coupled to a respective DRAM well. A control circuit applies select signals to gate electrodes of the first and second transistors. The control circuit includes respective shunt transistors that shunt the gate electrodes to the source regions of the first and second transistors when the transistors are turned off to isolate the respective DRAM wells from the external terminal regardless of the magnitude and polarity of a test voltage applied to the externally accessible terminal.

Claims

1. A control circuit for applying a select signal to a gate electrode of a pass transistor responsive to an access signal, the transistor having gate-source terminals coupled between first and second terminals, the control circuit comprising:

a shunt transistor having a gate terminal and a pair of source-drain terminals coupled between the first terminal and the gate electrode of the pass transistor;

a control transistor having a gate terminal coupled to receive the access signal, the control transistor having a pair of source-drain terminals coupled between the first terminal and the gate terminal of the shunt transistor;

a first switching transistor having a gate terminal coupled to receive the access signal, and a pair of source-drain terminals coupled between a supply voltage and the gate terminal of the control transistor; and

a second switching transistor having a gate terminal coupled to receive a compliment of the access signal, and a pair of source-drain terminals coupled between the supply voltage and the gate terminal of the shunt transistor.

2. The control circuit of claim 1 wherein the first switching transistor comprises a p-channel transistor.

3. The control circuit of claim 2 wherein the second switching transistor comprises a p-channel transistor.