Method and/or apparatus for reducing the complexity of H.264 B-frame encoding using selective reconstruction
First Claim
Patent Images
1. An apparatus comprising:
- an output circuit configured to generate an output data stream in response to (i) a first intermediate signal, (ii) a second intermediate signal, and (iii) a third intermediate signal;
a first processing circuit configured to generate said first intermediate signal in response to (i) a processed video signal and (ii) a prediction flag; and
a second processing circuit configured to generate (i) said processed video signal, (ii) said second intermediate signal and (iii) said third intermediate signal in response to an input video signal, wherein said second processing circuit is further configured to generate a prediction macroblock signal, said processed video signal, said second intermediate signal, and said third intermediate signal in further response to a fourth intermediate signal, wherein said fourth intermediate signal comprises (i) said first intermediate signal when in a first mode and (ii) an inverse guantized, inverse transformed version of said first intermediate signal when in a second mode.
10 Assignments
0 Petitions
Accused Products
Abstract
An apparatus comprising an output circuit, a first processing circuit and a second processing circuit. The output circuit may be configured to generate an output data stream in response to (i) a first intermediate signal, (ii) a second intermediate signal, and (iii) a third intermediate signal. The first processing circuit may be configured to generate the first intermediate signal in response to (i) a processed video signal and (ii) a prediction flag. The second processing circuit may be configured to generate (i) the processed video signal, (ii) the second intermediate signal and (iii) the third intermediate signal in response to an input video signal.
65 Citations
12 Claims
-
1. An apparatus comprising:
-
an output circuit configured to generate an output data stream in response to (i) a first intermediate signal, (ii) a second intermediate signal, and (iii) a third intermediate signal; a first processing circuit configured to generate said first intermediate signal in response to (i) a processed video signal and (ii) a prediction flag; and a second processing circuit configured to generate (i) said processed video signal, (ii) said second intermediate signal and (iii) said third intermediate signal in response to an input video signal, wherein said second processing circuit is further configured to generate a prediction macroblock signal, said processed video signal, said second intermediate signal, and said third intermediate signal in further response to a fourth intermediate signal, wherein said fourth intermediate signal comprises (i) said first intermediate signal when in a first mode and (ii) an inverse guantized, inverse transformed version of said first intermediate signal when in a second mode. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11)
-
-
12. An apparatus comprising:
-
means for generating an output data stream in response to (i) a first intermediate signal, (ii) a second intermediate signal, and (iii) a third intermediate signal; means for generating said first intermediate signal in response to (i) a processed video signal and (ii) a prediction flag; and means for generating (i) said processed video signal, (ii) said second intermediate signal and (iii) said third intermediate signal in response to an input video signal, wherein said means for generating said processed video signal, said second intermediate signal, and said third intermediate signal further generates a prediction macroblock signal and responds to a fourth intermediate signal, wherein said fourth intermediate signal comprises (i) said first intermediate signal when in a first mode and (ii) an inverse guantized, inverse transformed version of said first intermediate signal when in a second mode.
-
Specification