Stackable splice chip device

• US 7,310,471 B2
• Filed: 08/25/2005
• Issued: 12/18/2007
• Est. Priority Date: 08/25/2005
• Status: Expired due to Fees

• Current Assignee: Bison Patent Licensing, LLC
• Original Assignee: ADC Telecommunications Incorporated (TE Connectivity Limited)
• Inventors: Smrha, Mark, Bran De Leon, Oscar, Tinucci, Tom, Bayazit, Yilmaz
• Primary Examiner(s): CONNELLY, MICHELLE R
• Application Number:
  US11/212,470
• Publication Number:
  US 20070047891A1
• Time in Patent Office: 845 Days
• Field of Search: 385134-137, 385/99
• US Class Current: 385/135
• CPC Class Codes: G02B 6/44524 with frame parts or auxiliary devices mounted on the frame and collectively not covering a whole width of the frame or rack cassettes G02B6/4453
• CPC Class Codes: G02B 6/4454 with splices
• CPC Class Codes: G02B 6/4471 Terminating devices demountable connectors G02B6/3807; Cable clamps
• CPC Class Codes: G02B 6/44785 Cable clamps

Abstract

A splice tray arrangement including a tray and a splice chip arrangement. The splice chip arrangement including stackable splice chips defining channels for holding splice elements. Each of the splice chips including a mounting arrangement for mounting the splice chip at a mounting location on the tray, and a stacking arrangement for mounting the splice chip upon another splice chip.

Claims

1. A splice chip arrangement that mounts to a splice tray, the splice chip arrangement comprising:

a) a first splice chip and a second splice chip secured to one another in a stacked relationship, each of the first and second splice chips including;

i) a base having a first end and a second opposite end;

ii) a plurality of channels sized to receive splice elements; and

iii) first and second latch members located at the first and second ends of the splice chip, and first and second interlocking spaces defined by ledges located at the first and second ends of the base;

b) wherein the first end of the first splice chip is pivotally interconnected to the second end of the second splice chip; and

wherein the second end of the first splice chip is snap-fit to the first end of the second splice chip.

2. The arrangement of claim 1, wherein the latches and the interlocking spaces of the first and second splice chips are configured to detachably secure the splice chips in relation to one another such that each splice chip is selectively positionable in both of either one of a top position relative to the other splice chip or a bottom position relative to the other splice chip.

3. The arrangement of claim 2, wherein the interlocking space of the first and second splice chips is further is configured to selectively attach the splice chip arrangement to a tray.

4. A splice tray arrangement, comprising:

a) a tray having a splice chip mounting location;

b) a first splice chip positioned at the mounting location, the first splice chip including a plurality of splice holding structures, the first splice chip including mounting structure configured such that the first splice chip laterally slides into position at the mounting location; and

c) a second splice chip disposed on the first splice chip at the mounting location, the second splice chip including a plurality of splice holding structures;

d) wherein at least one of the first and second splice chips includes a release element for detaching the second splice chip from the first splice chip.

5. A splice chip, comprising:

a) a base having first and second opposite ends;

b) a plurality of channels sized to receive splice elements; and

c) a stacking arrangement, the stacking arrangement including;

i) mounting guides located at the opposite ends of the base, the mounting guides being configured to selectively mount the splice chip to another splice chip in a stacked relationship, the mounting guides further being configured to selectively mount the splice chip to a splice tray;

ii) latch members located at the opposite ends of the base, the latch members being configured to selectively receive another splice chip in a stacked relationship;

iii) alignment structure formed in a bottom surface of the base that aligns the splice chip relative to another splice chip when the splice chip is selectively mounted to another splice chip in a stacked relationship; and

iv) corresponding alignment structure located adjacent to the channels that aligns another splice chip relative to the splice chip when the splice chip selectively receives another splice chip in a stacked relationship.

6. The splice chip of claim 5, wherein the mounting guides extend beyond the opposite edges of the base, the mounting guides and the edges of the base defining interlocking spaces therebetween for selectively mounting the splice chip to another splice chip and a splice tray.

7. The splice chip of claim 5, wherein the alignment structure includes an alignment recess formed in the bottom surface of the base.

8. The splice chip of claim 5, wherein the corresponding alignment structure includes an alignment guide located adjacent to the channels.

9. The splice chip of claim 5, further including a release element for detaching another splice chip when splice chip selectively receives another splice chip.

10. A splice chip, comprising:

a) a base having first and second opposite ends;

b) a plurality of channels sized to receive splice elements; and

c) a stacking arrangement, the stacking arrangement including;

i) mounting guides located at the opposite ends of the base, the mounting guides being configured to selectively mount the splice chip to another splice chip in a stacked relationship, the mounting guides further being configured to selectively mount the splice chip to a splice tray;

ii) latch members located at the opposite ends of the base, the latch members being configured to selectively receive another splice chip in a stacked relationship;

iii) a recess formed in a bottom surface of the base; and

iv) a guide structure located adjacent to the channels;

v) wherein one of the recess and guide structure prevents lateral movement of the splice chip when the splice chip is selectively mounted to another spice chip in a stacked relationship.

11. A splice chip arrangement that mounts to a splice tray, the splice chip arrangement comprising:

a) a first splice chip and a second splice chip secured to one another in a stacked relationship, each of the first and second splice chips including;

i) a base having a first end and a second opposite end;

ii) a plurality of channels sized to receive splice elements;

b) wherein one of the first and second splice chips includes a latch member, and the other of the first and second splice chips includes a ledge projecting outward beyond the base to define an interlocking space, the latch member being pivotally engaged with the interlocking space to pivotally interconnect the first end of the first splice chip to the second end of the second splice chip;

c) and wherein the second end of the first splice chip is snap-fit to the first end of the second splice chip.

12. A splice chip arrangement that mounts to a splice tray, the splice chip arrangement comprising:

a) a first splice chip and a second splice chip secured to one another in a stacked relationship, each of the first and second splice chips including;

i) a base having a first end and a second opposite end; and

ii) a plurality of channels sized to receive splice elements;

b) wherein the first end of the first splice chip is pivotally interconnected to the second end of the second splice chip; and

wherein the second end of the first splice chip is snap-fit to the first end of the second splice chip; and

c) wherein a recess is formed in a bottom surface of the base of one of the first and second splice chips, and a guide structure is located adjacent to the channels of the other of the first and second splice chips, the recess of the one splice chip being configured to receive the guide structure of the other splice chip to prevent lateral movement of the splice chips relative to one another.

13. A splice chip arrangement that mounts to a splice tray, the splice chip arrangement comprising:

a) a first splice chip and a second splice chip secured to one another in a stacked relationship, each of the first and second splice chips including;

i) a base having a first end and a second opposite end; and

ii) a plurality of channels sized to receive splice elements;

b) wherein the first end of the first splice chip is pivotally interconnected to the second end of the second splice chip; and

wherein the second end of the first splice chip is snap-fit to the first end of the second splice chip; and

c) wherein a recess is formed in a bottom surface of the base of one of the first and second splice chips, and an alignment guide is located adjacent to the channels of the other of the first and second splice chips, the recess of the one splice chip being configured to receive the alignment guide of the other splice chip to align the splice chips in relation to one another.