Memory hub tester interface and method for use thereof
First Claim
Patent Images
1. A memory hub, comprising:
- a test command interface for coupling to a test bus and through which test command packets are received, the test command interface configured to latch the test command packets in response to a test clock signal having a test clock frequency;
a memory device interface for coupling memory device command, address and data signals to a memory device, the memory device interface configured to provide the memory device command, address and data signals to the memory device in response to a memory device clock signal having a memory device clock frequency;
a test command latch coupled to the test command interface and the memory device interface to latch a memory device command of a received test command packet and provide memory device command signals to the memory device in accordance with the memory device command to test the memory device;
a test address generator coupled to the test command interface and the memory device interface to generate the memory device address signals for the memory device in accordance with the received test command packet;
a test data generator coupled to the test command interface and the memory device interface to generate the memory device data signal for the memory device in accordance with the received test command packet; and
an error detect circuit coupled to the test bus and configured to compare expected data corresponding to the memory device data signal and data read from the memory device and further configured to provide a signal indicative of the results from the comparison over the test bus.
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Accused Products
Abstract
A memory hub including a memory test bridge circuit for testing memory devices. Test command packets are coupled from a tester to the memory hub responsive to a test clock signal having a test clock frequency. The test bridge circuit generates memory device command, address, and data signals in accordance with the test command packets, and the memory device command, address, and data signals are provided to a memory device under test that is coupled to the memory hub responsive to a memory device clock signal having a memory device clock frequency.
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Citations
52 Claims
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1. A memory hub, comprising:
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a test command interface for coupling to a test bus and through which test command packets are received, the test command interface configured to latch the test command packets in response to a test clock signal having a test clock frequency; a memory device interface for coupling memory device command, address and data signals to a memory device, the memory device interface configured to provide the memory device command, address and data signals to the memory device in response to a memory device clock signal having a memory device clock frequency; a test command latch coupled to the test command interface and the memory device interface to latch a memory device command of a received test command packet and provide memory device command signals to the memory device in accordance with the memory device command to test the memory device; a test address generator coupled to the test command interface and the memory device interface to generate the memory device address signals for the memory device in accordance with the received test command packet; a test data generator coupled to the test command interface and the memory device interface to generate the memory device data signal for the memory device in accordance with the received test command packet; and an error detect circuit coupled to the test bus and configured to compare expected data corresponding to the memory device data signal and data read from the memory device and further configured to provide a signal indicative of the results from the comparison over the test bus. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11)
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12. A memory hub, comprising:
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a test circuit having a test command packet latch to latch test command packets including test command information, the test circuit latching the test command packets responsive to a test clock signal having a test clock frequency, the test interface circuit further having a test command circuit coupled to the test command packet latch to generate memory device command, address and data signals for testing a memory device in accordance with the test command information; a memory device interface circuit coupled to the test circuit to couple the memory device command, address and data signals to a memory device under test, the memory device interface configured to provide the memory device command, address and data signals to the memory device under test responsive to a memory device clock signal having a memory device clock frequency; and an error detect circuit coupled to the memory device interface circuit and the test circuit to compare expected data corresponding to the memory device data signal and data read from the memory device under test, the error detect circuit configured to provide a signal indicative of the results from the comparison for access through the test circuit. - View Dependent Claims (13, 14, 15, 16, 17, 18, 19, 20, 21, 22)
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23. A memory module, comprising:
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a plurality of memory devices; a memory device bus coupled to the memory devices; and a memory hub coupled to the memory device bus, the memory hub comprising; a test circuit having a test command packet latch to latch test command packets including test command information, the test circuit latching the test command packets responsive to a test clock signal having a test clock frequency, the test interface circuit further having a test command circuit coupled to the test command packet latch to generate memory device command, address and data signals for testing a memory device in accordance with the test command information; a memory device interface circuit coupled to the test circuit to couple the memory device command, address and data signals to a memory device under test, the memory device interface configured to provide the memory device command, address and data signals to the memory device under test responsive to a memory device clock signal having a memory device clock frequency; and an error detect circuit coupled to the memory device interface circuit and the test circuit to compare expected data corresponding to the memory device data signal and data read from the memory device under test, the error detect circuit configured to provide a signal indicative of the results from the comparison for access through the test circuit. - View Dependent Claims (24, 25, 26, 27, 28, 29, 30, 31, 32)
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33. A memory test apparatus, comprising:
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a memory tester for providing memory test command packets to test memory devices; a memory test bus coupled to the memory tester; a memory module coupled to the memory test bus for testing, the memory module comprising; a plurality of memory devices; a memory device bus coupled to the memory devices; and a memory hub coupled to the memory device bus, the memory hub comprising; a test circuit having a test command packet latch to latch test command packets including test command information, the test circuit latching the test command packets responsive to a test clock signal having a test clock frequency, the test interface circuit further having a test command circuit coupled to the test command packet latch to generate memory device command, address and data signals for testing a memory device in accordance with the test command information; a memory device interface circuit coupled to the test circuit to couple the memory device command, address and data signals to a memory device under test, the memory device interface configured to provide the memory device command, address and data signals to the memory device under test responsive to a memory device clock signal having a memory device clock frequency; and an error detect circuit coupled to the memory device interface circuit and the test circuit to compare expected data corresponding to the memory device data signal and data read from the memory device under test, the error detect circuit configured to provide a signal indicative of the results from the comparison for access through the test circuit. - View Dependent Claims (34, 35, 36, 37, 38, 39, 40, 41, 42)
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43. A memory test apparatus, comprising:
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a memory tester for providing memory test command packets to test memory devices; a memory test bus coupled to the memory tester; a memory module coupled to the memory test bus for testing, the memory module comprising; a plurality of memory devices; a memory device bus coupled to the memory devices; and a memory hub coupled to the memory device bus, the memory hub comprising; a plurality of memory devices; a memory device bus coupled to the memory devices; and a memory hub coupled to the memory device bus, the memory hub comprising; a memory test bridge circuit having a tester interface through which test command packets are received responsive to a test clock signal and further having a memory interface coupled to the tester interface through which memory commands corresponding to a test command packet are provided to at least one memory device responsive to a memory clock signal; and an error detect circuit coupled to the memory test bridge circuit for comparing expected data received by the memory test bridge circuit to read data returned from the memory device in response to a memory command, the error detect circuit operable to generate in response to the comparison pass/fail data indicative of whether the read data matches the expected data. - View Dependent Claims (44, 45, 46, 47, 48, 49, 50, 51, 52)
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Specification